V62SLASH12615-01XE-R datasheet(67/98 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-19. MII Interrupt Control Register (MICR), Address 0x11 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

INTEN

0, RW

Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR register.

1 = Enable event based interrupts

0 = Disable event based interrupts

INT_OE

0, RW

Interrupt Output Enable:

Enable interrupt events to signal via the PWR_DOWN/INT pin by

configuring the PWR_DOWN/INT pin as an output.

1 = PWR_DOWN/INT is an Interrupt Output

0 = PWR_DOWN/INT is a Power Down Input

5.6.2.3

MII Interrupt Status and Miscellaneous Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 5-20. MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

ED_INT

0, RO/COR

Energy Detect interrupt:

1 = Energy detect interrupt is pending and is cleared by the current

read

0 = No energy detect interrupt pending

LINK_INT

0, RO/COR

Change of Link Status interrupt:

1 = Change of link status interrupt is pending and is cleared by the

current read

0 = No change of link status interrupt pending

SPD_INT

0, RO/COR

Change of speed status interrupt:

1 = Speed status change interrupt is pending and is cleared by the

current read

0 = No speed status change interrupt pending

DUP_INT

0, RO/COR

Change of duplex status interrupt:

1 = Duplex status change interrupt is pending and is cleared by the

current read

0 = No duplex status change interrupt pending

ANC_INT

0, RO/COR

Auto-Negotiation Complete interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared by

the current read

0 = No Auto-negotiation complete interrupt pending

FHF_INT

0, RO/COR

False Carrier Counter half-full interrupt:

1 = False carrier counter half-full interrupt is pending and is cleared by

the current read

0 = No false carrier counter half-full interrupt pending

RHF_INT

0, RO/COR

Receive Error Counter half-full interrupt:

1 = Receive error counter half-full interrupt is pending and is cleared

by the current read

0 = No receive error carrier counter half-full interrupt pending

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

ED_INT_EN

0, RW

Enable Interrupt on energy detect event

LINK_INT_EN

0, RW

Enable Interrupt on change of link status

V62/12615-01XE-R Datasheet(PDF) 67 Page - Texas Instruments

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