V62SLASH12615-01XE-R datasheet(73/98 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

5.6.2.11 CD Test and BIST Extensions Register (CDCTRL1)

Table 5-28. CD Test and BIST Extensions Register (CDCTRL1), Address 0x1B

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

BIST_ERROR_CO

UNT

0, RO

BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This value

will reset when Packet BIST is restarted. The counter sticks when it

reaches its max count.

7:6

RESERVED

0, RW

RESERVED: Must be zero

BIST_CONT_MOD E

0, RW

Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing. This

is used in conjunction with the BIST controls in the PHYCR Register

(0x19h). For 10Mb operation, jabber function must be disabled, bit 0

of the 10BTSCR (0x1Ah), JABBER_DIS = 1.

CDPATTEN_10

0, RW

CD Pattern Enable for 10Mb:

1 = Enabled

0 = Disabled

RESERVED

0, RW

RESERVED: Must be zero

10MEG_PATT_GA P

0, RW

Defines gap between data or NLP test sequences:

1 = 15 µs

0 = 10 µs

1:0

CDPATTSEL[1:0]

00, RW

CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10MHz sine wave) for harmonic

distortion testing

5.6.2.12 Energy Detect Control (EDCR)

Table 5-29. Energy Detect Control (EDCR), Address 0x1D

BIT

BIT NAME

DEFAULT

DESCRIPTION

ED_EN

0, RW

Energy Detect Enable:

Allow Energy Detect Mode.

When Energy Detect is enabled and Auto-Negotiation is disabled via

the BMCR register, Auto-MDIX should be disabled via the PHYCR

ED_AUTO_UP

1, RW

Energy Detect Automatic Power Up:

Automatically begin power up sequence when Energy Detect Data

Threshold value (EDCR[3:0]) is reached. Alternatively, device could

be powered up manually using the ED_MAN bit (ECDR[12]).

ED_AUTO_DOWN

1, RW

Energy Detect Automatic Power Down:

Automatically begin power down sequence when no energy is

detected. Alternatively, device could be powered down using the

ED_MAN bit (EDCR[12]).

ED_MAN

0, RW/SC

Energy Detect Manual Power Up/Down:

Begin power up/down sequence when this bit is asserted. When set,

the Energy Detect algorithm will initiate a change of Energy Detect

state regardless of threshold (error or data) and timer values. In

managed applications, this bit can be set after clearing the Energy

Detect interrupt to control the timing of changing the power state.

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