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DP83821 Datasheet(PDF) 37 Page - National Semiconductor (TI) |
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DP83821 Datasheet(HTML) 37 Page - National Semiconductor (TI) |
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37 / 86 page  37 www.national.com 4.0 Register Set (Continued) 4.1.8 Configuration Subsystem Identification Register The CFGSID allows system software to distinguish between different subsystems based on the same PCI silicon. The values in this register can be loaded from the EEPROM if configuration is enabled. 4.1.9 Boot ROM Configuration Register 4.1.10 Capabilities Pointer Register This register stores the capabilities linked list offset into the PCI configuration space. Tag: CFGSID Size: 32 bits Hard Reset: ? Offset: 2Ch Access: Read Only Soft Reset: unchanged bit tag description usage 31-16 SDEVID Subsystem Device ID Loaded from the EEPROM 15-0 SVENID Subsystem Vendor ID Loaded from the EEPROM Tag: CFGROM Size: 32 bits Hard Reset: 00000000h Offset: 30h Access: Read Write Soft Reset: unchanged bit tag description usage 31-16 ROMBASE ROM Base Address Set to the base address for the boot ROM. 15-11 ROMSIZE ROM Size Read only. Set to 0 indicating a requirement for 32K bytes of Boot ROM space 10-1 Unused unused (reads return 0) 0 ROMEN ROM Enable This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83821 to share the address decode logic between the boot ROM and itself. The BIOS will copy the contents of the boot ROM to system RAM before executing it. Set to 1 enables the address decode for boot ROM disabling access to operational target registers. Tag: CAPPTR Size: 32 bits Hard Reset: 00000040h Offset: 34h Access: Read Only Soft Reset: unchanged bit tag description usage 31-8 unused (reads return 0) 7-0 CLOFS Capabilities List Offset Offset into PCI configuration space for the location of the first item in the Capabilities Linked List, set to 40h to point to the PMCAP register. |
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