DP83821 datasheet(69/86 Pages) NSC

69 / 86 page

www.national.com

4.0 Register Set (Continued)

4.2.35 VLAN/IP Transmit Control Register

This register allows enabling of the various VLAN tag handling features and IP checksum offload features.

4.2.36 VLAN Data Register

This register contains data for VLAN tag insertion and detection.

4.2.37 Clockrun Control/Status Register

Tag: VTCR

Size: 32 bits

Hard Reset: 00000000h

Offset: 00C0h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-4

unused

PPCHK

Per-Packet

Checksum

Generation

Enables IP/TCP/UDP Checksum generation on a per-packet basis. Uses individual

enable controls from the EXTSTS field of the packet descriptor.

GCHK

Global Checksum

Generation

Enables IP/TCP/UDP Checksum generation on all transmit packets.

VPPTI

VLAN Per-Packet

Tag Insertion

Insert VLAN tag in on a per-packet basis. Uses the VLAN Data Register VLAN type field

for the VLAN type. Uses the user_priority, CFI and VLAN ID fields from the EXTSTS field

of the packet descriptor.

VGTI

VLAN Global Tag

Insertion

Insert VLAN tag in all transmit packets. Uses the VLAN Data Register data for the 32-bit

VLAN tag to be inserted.

Tag: VDR

Size: 32 bits

Hard Reset: 00000081h

Offset: 00C4h

Access: Read Write

Soft Reset: 00000081h

bit

tag

description

usage

31-16

VTCI

VLAN Tag Control

Information Field

This field is the 2-octet VLAN TCI field. It is used by the transmitter during Global Tag

Insertion. It contains the VLAN user_priority, CFI and VID (VLAN Identifier) fields. It is not

used by the receiver.

15-0

VTYPE

VLAN Type Field

This field is the 2-octet VLAN type field. By default this contains the 802.1QTag Type of

81-00. In order to represent the order the bytes will be shifted on the wire, it actually

contains a value of 0081h. This field is used by the transmitter for Global Tag Insertion

and by the receiver for Tag detection.

Tag: CCSR

Size: 32 bits

Hard Reset: 00000000h

Offset: 00CCh

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-16

unused (reads return 0)

PMESTS

PME Status

Sticky bit which represents the state of the PME/CLKRUN logic, regardless of the state of

the PMEEN bit. Mirrored from PCI configuration register PMCSR. Writing a 1 to this bit

clears it.

14-9

unused (reads return 0)

PMEEN

PME Enable

When set to 1, this bit enabled the assertion of the PMEN pin. When 0, the PMEN pin is

forced to be inactive. This value can be loaded from the EEPROM. Mirrored from PCI

configuration register PMCSR.

7-1

unused (reads return 0)

CLKRUN_EN CLKRUN Enable When set to 1, this bit enables the CLKRUN logic and allows the assertion of the

CLKRUN_N pin. When 0, the CLKRUN function is disabled.

DP83821 Datasheet(PDF) 69 Page - National Semiconductor (TI)

DP83821 Datasheet(HTML) 69 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL