DP83821 datasheet(47/86 Pages) NSC

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4.0 Register Set (Continued)

RXDESC3

Rx Descriptor for Priority

Queue 3

This event is signaled after a receive descriptor with the INTR bit set in the

CMDSTS field has been updated.

RXDESC2

Rx Descriptor for Priority

Queue 2

This event is signaled after a receive descriptor with the INTR bit set in the

CMDSTS field has been updated.

RXDESC1

Rx Descriptor for Priority

Queue 1

This event is signaled after a receive descriptor with the INTR bit set in the

CMDSTS field has been updated.

RXDESC0

Rx Descriptor for Priority

Queue 0

This event is signaled after a receive descriptor with the INTR bit set in the

CMDSTS field has been updated.

TXRCMP

Transmit Reset Complete

Indicates that a requested transmit reset operation is complete.

RXRCMP

Receive Reset Complete

Indicates that a requested receive reset operation is complete.

DPERR

Detected Parity Error

This bit is set whenever CFGCS:DPERR is set, but cleared (like all other

ISR bits) when the ISR register is read.

SSERR

Signaled System Error

The DP83821 signaled a system error on the PCI bus.

RMABT

Received Master Abort

The DP83821 received a master abort generated as a result of target not

responding.

RTABT

Received Target Abort

The DP83821 received a target abort on the PCI bus.

RXSOVR

Rx Status FIFO Overrun

Set when an overrun condition occurs on the Rx Status FIFO.

HIBINT

High Bits Interrupt Set

A logical OR of bits 22-16

PHY

Phy interrupt

Set to 1 when interrupt is generated due to change in phy status.

PME

Power Management Event

Set when WOL conditioned detected

SWI

Software Interrupt

Set whenever the SWI bit in the CR register is set.

MIB

MIB Service

Set when one of the enabled management statistics has reached its

interrupt threshold.

TXURN

Tx Underrun

Set when a transmit data FIFO underrun condition occurs.

TXIDLE

Tx Idle

This event is signaled when the transmit state machine enters the idle state

from a non-idle state. This will happen whenever the state machine

encounters an "end-of-list" condition (NULL link field or a descriptor with

OWN clear).

TXERR

Tx Packet Error

This event is signaled after the last transmit descriptor in a failed

transmission attempt has been updated with valid status.

TXDESC

Tx Descriptor

This event is signaled after a transmit descriptor with the INTR bit set in the

CMDSTS field has been updated. If priority queueing is enabled, this bit will

be set when any of the TXDESC0-3 bits are set.

TXOK

Tx Packet OK

This event is signaled after the last transmit descriptor in a successful

transmission attempt has been updated with valid status

RXORN

Rx Overrun

Set when a receive data FIFO overrun condition occurs.

RXIDLE

Rx Idle

This event is signaled when the receive state machine enters the idle state

from a running state. This will happen whenever the state machine

encounters an "end-of-list" condition (NULL link field or a descriptor with

OWN set).

RXEARLY

Rx Early Threshold

Indicates that the initial Rx Drain Threshold has been met by the incoming

packet, and the transfer of the number of bytes specified by the DRTH field

in the RXCFG register has been completed by the receive DMA engine.

This interrupt condition will occur only once per packet.

RXERR

Rx Packet Error

This event is signaled after the last receive descriptor in a failed packet

reception has been updated with valid status.

RXDESC

Rx Descriptor

This event is signaled after a receive descriptor with the INTR bit set in the

CMDSTS field has been updated. If priority queueing is enabled, this bit will

be set when any of the RXDESC0-3 bits are set.

RXOK

Rx OK

Set by the receive state machine following the update of the last receive

descriptor in a good packet.

DP83821 Datasheet(PDF) 47 Page - National Semiconductor (TI)

DP83821 Datasheet(HTML) 47 Page - National Semiconductor (TI)

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