DP83821 datasheet(14/86 Pages) NSC

14 / 86 page

3.0 Functional Description (Continued)

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Figure 3-7 Master Write Operation

3.3.5 Configuration Access

Configuration register accesses are similar to Target reads

and writes in that they are single data word transfers and

are initiated by the system. For the system to initiate a

Configuration access, it must also generate IDSELN as

well as the correct Command (1010b or 1011b) during the

Address phase. The DP83821 will respond as it does

during Target operations.

Note: Configuration reads must be 32-bits wide, but writes may access individual

bytes.

3.4 Packet Buffering

The DP83821 incorporates two independent FIFOs for

transferring data to/from the system interface and from/to

the network. The FIFOs, providing temporary storage of

data, free the host system from the real-time demands of

the network.

The way in which the FIFOs are emptied and filled is

controlled by the FIFO threshold values in the TXCFG and

RXCFG registers (See Sections 4.2.12 and 4.2.16). These

values determine how full or empty the FIFOs must be

before the device requests the bus. Additionally, there is a

threshold value that determines how full the transmit FIFO

must

before

beginning

transmission.

Once

the

DP83821 requests the bus, it will attempt to empty or fill

the FIFOs as allowed by the respective MXDMA settings in

TXCFG and RXCFG.

3.4.1 Transmit Buffer Manager

The buffer management scheme used on the DP83821

allows quick, simple and efficient use of the frame buffer

memory. The buffer management scheme uses separate

buffers and descriptors for packet information. This allows

effective transfers of data to the transmit buffer manager by

simply transferring the descriptor information to the

transmit queue. Refer to the Buffer Management section

for complete information.

The Tx Buffer Manager DMAs packet data from PCI

memory space and places it in the 8KB transmit FIFO, and

pulls data from the FIFO to send to the Tx MAC. Multiple

packets may be present in the FIFO, allowing packets to be

transmitted with minimum interframe gap. The way in

which the FIFO is emptied and filled is controlled by the

FIFO threshold values in the TXCFG register: FLTH (Tx Fill

Threshold), and DRTH (Tx Drain Threshold). Additionally,

once the DP83821 requests the bus, it will attempt to fill the

FIFO as allowed by the MXDMA setting in the TXCFG

3.4.2 Transmit Priority Queueing

The Tx Buffer Manager process also supports priority

queueing of transmit packets. It handles this by drawing

from four separate descriptor lists to fill the internal FIFO. If

packets are available in the higher priority queues, they will

be loaded into the FIFO before those of lower priority.

3.4.3 Receive Buffer Manager

The Rx Buffer Manager uses the same buffer management

scheme as used for transmits. Refer to the Buffer

Management section for complete information.

The Rx Buffer Manager retrieves packet data from the Rx

MAC and places it in the 32KB receive data FIFO, and

pulls data from the FIFO for DMA to PCI memory space.

The Rx Buffer Manager maintains a status FIFO, allowing

up to 32 packets to reside in the FIFO at once. Similar to

the transmit FIFO, the receive FIFO is controlled by the

FIFO

threshold

value

RXCFG:DRTH

(Rx

Drain

Threshold). This value determines the number of long

words written into the FIFO from the MAC unit before a

DMA request for system memory occurs. Once the

DP83821 gets the bus, it will continue to transfer the long

words from the FIFO until the data in the FIFO is less than

one long word, or has reached the end of the packet, or the

max DMA burst size is reached (RXCFG register:MXDMA).

3.4.4 Receive Priority Queueing

The Rx Buffer Manager process also supports priority

queueing of receive packets. It handles this by placing

packets on up to four separate descriptor lists when

emptying the internal FIFO. The Rx Buffer Manager uses

information in a VLAN tag to determine packet priority.

Addr

Data

CLK

FRAMEN

AD[31:0]

C/BEN[3:0]

REQN

GNTN

IRDYN

TRDYN

DEVSELN

PAR

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