DP83821 datasheet(65/86 Pages) NSC

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4.0 Register Set (Continued)

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4.2.27 Management Information Base Registers

The counters provide a set of statistics compliant with the

following management specifications: MIB II, Ether-like

MIB, and IEEE MIB. The values provided are accessed

through the various registers as shown below. All MIB

counters are cleared to 0 when read.

Due to cost and space limitations, the counter bit widths

provided in the DP83821 MIB are less than the bit widths

called for in the above specifications. It is assumed that

management agent software will maintain a set of fully

compliant statistic values ("software" counters), utilizing the

hardware counters to reduce the frequency at which these

"software" counters must be updated. Sizes for specific

hardware statistic counters were chosen such that the

count values will not roll over in less than 30 ms if

incremented at the theoretical maximum rates described in

the

above

specifications.

However,

given

that

the

theoretical maximum counter rates do not represent

realistic network traffic and events, the actual rollover rates

for the hardware counters are more likely to be on the

order of several seconds. The hardware counters are

updated automatically by the MAC on the occurrence of

each event.

Table 4-3 MIB Registers

offset

tag

size

warning

(MS bits)

description

0060h

RXErroredPkts

Packets received with errors. This counter is incremented for each

packet received with errors. This count includes packets which are

automatically rejected from the FIFO due to both wire errors and

FIFO overruns.

0064h

RXFCSErrors

Packets received with frame check sequence errors. This counter is

incremented for each packet received with a Frame Check

Sequence error (bad CRC).

Note: For the MII interface, an FCS error is defined as a resulting

invalid CRC after CRS goes invalid and an even number of bytes

have been received.

0068h

RXMsdPktErrors

Packets missed due to FIFO overruns. This counter is incremented

for each receive aborted due to data or status FIFO overruns

(insufficient buffer space).

006Ch

RXFAErrors

Packets received with frame alignment errors. This counter is

incremented for each packet received with a Frame Check

Sequence error (bad CRC).

Note: For the MII interface, an FAE error is defined as a resulting

invalid CRC on the last full octet, and an odd number of nibbles have

been received (Dribble nibble condition with a bad CRC).

0070h

RXSymbolErrors

Packets received with one or more symbol errors. This counter is

incremented for each packet received with one or more symbol

errors detected.

Note: For the MII interface, a symbol error is indicated by the

RX_ER signal becoming active for one or more clocks while the

RX_DV signal is active (during valid data reception).

0074h

RXFrameTooLong

Packets received with length greater than 1518 bytes (too long

packets). This counter is incremented for each packet received with

greater than the 802.3 standard maximum length of 1518 bytes.

0078h

RXIRLErrors

Packets received with In Range Length errors. This counter

increments for packets received with a MAC length/type value

between 64 and 1518 bytes, inclusive, that does not match the

number of bytes received. This counter also increments for packets

with a MAC length/type field of less than 64 bytes and more than 64

bytes received.

007Ch

RXBadOpcodes

Packets received with a valid MAC control type and an opcode for a

function that is not supported by the device.

0080h

RXPauseFrames

MAC control Pause frames received.

0084h

TXPauseFrames

MAC control Pause frames transmitted.

0088h

TXSQEErrors

Loss of collision heartbeat during transmission. This counter is

incremented when the collision heartbeat pulse is not detected by

the PMD after a transmission.

DP83821 Datasheet(PDF) 65 Page - National Semiconductor (TI)

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