DP83821 datasheet(53/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.17 Priority Queueing Control Register

This register allows control of Priority Queueing features.

ALP

Accept Long Packets

When set to 1, all packets > 1518 bytes in length and <= 65527 bytes will

be treated as normal receive packets, and will not be tagged as long or

error packets. All packets > 65527 bytes in length will be truncated at

65528 bytes and either rejected from the FIFO, or tagged as long packets.

Care must be taken when accepting long packets to ensure that buffers

provided are of adequate length. When ALP is set to 0, packets larger than

1518 bytes (CRC inclusive) will be truncated at 1514 bytes, and rejected if

possible.

AIRL

Accept In-Range Length

Errored Packets

When set to 1, packets with Length/Type fields that do not match the data

length of the packet will be accepted. When set to 0, packets with

Length/Type fields that do not match the data length of the packet will be

rejected. In-Range Length checking only occurs if the Length/Type field is a

valid length.

25-23

unused

22-20

MXDMA

Max DMA Burst Size per Rx

DMA Burst

This field sets the maximum size of receive DMA data bursts according to

the following table:

000 = 256 32-bit words (1024 bytes)

001 = 2 32-bit words (8 bytes)

010 = 4 32-bit words (16 bytes)

011 = 8 32-bit words (32 bytes)

100 = 16 32-bit words (64 bytes)

101 = 32 32-bit words (128 bytes)

110 = 64 32-bit words (256 bytes)

111 = 128 32-bit word (512 bytes)

19-6

unused

5-1

DRTH

Rx Drain Threshold

Specifies the drain threshold in units of 8 bytes. When the number of bytes

in the receive FIFO reaches this value (times 8), or the FIFO contains a

complete packet, the receive bus master state machine will begin the

transfer of data from the FIFO to host memory. Care must be taken when

setting DRTH to a value lower than the number of bytes needed to

determine if packet should be accepted or rejected. In this case, the packet

might be rejected after the bus master operation to begin transferring the

packet into memory has begun. When this occurs, neither the OK bit or any

error status bit in the descriptor’s cmdsts will be set. A value of 0 prevents

draining of the packet until it is completely received.

This value is also used to compare with the accumulated packet length for

early receive indication. When the accumulated packet length meets or

exceeds the DRTH value, the RXEARLY interrupt condition is generated. A

value of 0 prevents the RXEARLY interrupt.

unused.

Tag: PQCR

Size: 32 bits

Hard Reset: 00000000h

Offset: 003Ch

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-4

unused

DP83821 Datasheet(PDF) 53 Page - National Semiconductor (TI)

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