DP83821 datasheet(52/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.14 Receive Descriptor Pointer Register

This register points to the current Receive Descriptor.

4.2.15 Reserved

This register is reserved and must always be read and written as 00000000h.

4.2.16 Receive Configuration Register

This register is used to set the receive configuration for DP83821. Receive properties such as accepting error packets,

runt packets, setting the receive drain threshold etc. are controlled here

Tag: RXDP

Size: 32 bits

Hard Reset: 00000000h

Offset: 0030h

Access: Read Write

Soft Reset: 00000000h

bit

tag

description

usage

31-3

RXDP

Receive Descriptor Pointer

The current value of the receive descriptor pointer. When the receive state

machine is idle, software must set RXDP to the address of an available

receive descriptor. While the receive state machine is active, RXDP will

follow the state machine as it advances through a linked list of available

descriptors. If the link field of the current receive descriptor is NULL

(signifying the end of the list), RXDP will not advance, but will remain on the

current descriptor. Any subsequent writes to the RXE bit of the CR register

will cause the receive state machine to reread the link field of the current

descriptor to check for new descriptors that may have been appended to

the end of the list. Software should not write to this register unless the

receive state machine is idle. Receive descriptors must be aligned on 64-bit

boundaries (A2-A0 must be zero). A 0 written to RXDP followed by a

subsequent write to RXE will cause the receiver to enter silent RX mode,

for use during WOL. In this mode packets will by received and buffered in

FIFO, but no DMA to system memory will occur. The packet data may be

recovered from the FIFO by writing a valid descriptor address to RXDP and

then strobing RXE.

2-0

unused

Tag: RXCFG

Size: 32 bits

Hard Reset: 00000004h

Offset: 0038h

Access: Read Write

Soft Reset: 00000004h

bit

tag

description

usage

AEP

Accept Errored Packets

When set to 1, all packets with CRC or alignment errors will be accepted.

When set to 0, all packets with CRC or alignment errors will be rejected if

possible. Note that depending on the type of error, some packets may be

received with errors, regardless of the setting of AEP. These errors will be

indicated in the CMDSTS field of the last descriptor in the packet.

ARP

Accept Runt Packets

When set to 1, all packets under 64 bytes in length without errors are

accepted. When this bit is 0, all packets less than 64 bytes in length will be

rejected if possible.

STRIPCRC

Strip CRC

When set to a 1, the CRC will be stripped from the receive packet and the

byte count adjusted appropriately.

RX_FD

Receive Full Duplex

When set to 1, data received simultaneously to a local transmission (such

as during a PMD loopback or full duplex operation) will be accepted as

valid received data. When set to 0 (default), all data received simultaneous

to a local transmit will be rejected. This bit must be set to 1 for PMD

loopback and full duplex operation.

DP83821 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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