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DP83821 Datasheet(PDF) 40 Page - National Semiconductor (TI) |
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DP83821 Datasheet(HTML) 40 Page - National Semiconductor (TI) |
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40 / 86 page  40 www.national.com 4.0 Register Set (Continued) 4.2 Operational Registers The DP83821 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. When mapped to I/O space, a 256 byte window allows access to all the Operational Registers (00-FCh). When mapped into PCI memory space, a 4096 byte window is enabled. In addition to access to Operational Registers, the PCI Configuration Registers can be read at addresses 200-2FCh. Other addresses provide aliased access to Operational Registers or read-only PCI Configuration Registers. Table 4-2 Operational Register Map offset tag description access 00h CR Command Register R/W 04h CFG Configuration Register R/W 08h MEAR EEPROM Access Register R/W 0Ch PTSCR PCI Test Control Register R/W 10h ISR Interrupt Status Register RO 14h IMR Interrupt Mask Register R/W 18h IER Interrupt Enable Register R/W 1Ch IHR Interrupt Holdoff Register R/W 20h TXDP Transmit Descriptor Pointer Register R/W 24h Reserved R/W 28h TXCFG Transmit Configuration Register R/W 2Ch GPIOR General Purpose I/O Control Register R/W 30h RXDP Receive Descriptor Pointer Register R/W 34h Reserved R/W 38h RXCFG Receive Configuration Register R/W 3Ch PQCR Priority Queueing Control Register R/W 40h WCSR Wake on LAN Control/Status Register R/W 44h PCR Pause Control/Status Register R/W 48h RFCR Receive Filter/Match Control Register R/W 4Ch RFDR Receive Filter/Match Data Register R/W 50h BRAR Boot ROM Address R/W 54h BRDR Boot ROM Data R/W 58h SRR Silicon Revision Register RO 5Ch MIBC Management Information Base Control Register R/W 60-88h MIB Management Information Base Data Registers RO 8C-9Ch Reserved A0h TXDP1 Transmit Descriptor Pointer Priority 1 Register R/W A4h TXDP2 Transmit Descriptor Pointer Priority 2 Register R/W A8h TXDP3 Transmit Descriptor Pointer Priority 3 Register R/W ACh Reserved B0h RXDP1 Receive Descriptor Pointer Priority 1 Register R/W B4h RXDP2 Receive Descriptor Pointer Priority 2 Register R/W B8h RXDP3 Receive Descriptor Pointer Priority 3 Register R/W BCh VRCR VLAN/IP Receive Control Register R/W C0h VTCR VLAN/IP Transmit Control Register R/W C4h VDR VLAN Data register R/W C8 Reserved |
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