DP83821 datasheet(11/86 Pages) NSC

11 / 86 page

3.0 Functional Description (Continued)

www.national.com

3.2 PCI Bus Interface

The DP83821 implements the Peripheral Component

Interconnect (PCI) bus interface as defined in PCI Local

Bus Specification Version 2.2. When internal register are

being accessed the DP83821 acts as a PCI target (slave).

When accessing host memory for descriptor or packet data

transfer, the DP83821 acts as a PCI bus master.

All required pins and functions are implemented. The

optional interface pin INTA for support of interrupt requests

is implemented as well. The bus interface supports 32-bit

and 33Mhz operation.

For more information, refer to the PCI Local Bus

Specification version 2.2, December 18, 1998.

3.2.1 Byte Ordering

The DP83821 can be configured to order the bytes of data

on the AD[31:0] bus to conform to Little Endian or Big

Endian ordering through the use of the CFG:BEM bit. Byte

ordering only affects bus mastered packet data transfers in

32-bit mode. Register information remains bit aligned (i.e.

AD[31] maps to bit 31 in any register space, AD[0] maps to

bit 0, etc.) when registers are accessed with 32-bit

operations. Bus mastered transfers of buffer descriptor

information also remain bit aligned.

When configured for Little Endian (CFG:BEM=0), the byte

orientation for receive and transmit data and descriptors in

system memory is as follows:

Figure 3-2 Little Endian Byte Ordering

When configured for big-endian mode (CFG:BEM=1), the

byte orientation for receive

and transmit data and

descriptors in system memory is as follows:

Figure 3-3 Big Endian Byte Ordering

3.2.2 Interrupt Control

Interrupts are performed by asynchronously asserting the

INTAN pin. This pin is an open drain output. The source of

the interrupt can be determined by reading the Interrupt

Status Register (ISR) (See Section 4.2.6). One or more

bits in the ISR will be set, denoting all currently pending

interrupts. Reading of the ISR clears ALL bits. Masking of

specific interrupts can be accomplished by using the

Interrupt Mask Register

(IMR) (See

Section

4.2.7).

Assertion of INTAN can be prevented by clearing the

Interrupt Enable bit in the Interrupt Enable Register (See

Section 4.2.8). This allows the system to defer interrupt

processing as needed.

3.2.3 Latency Timer

The Latency Timer described in CFGLAT:LAT (See Section

4.1.4) defines the maximum number of bus clocks that the

device will hold the bus. Once the device gains control of

the bus and issues FRAMEN, the Latency Timer will begin

counting down. If GNTN is deasserted before the DP83821

has finished with the bus, the device will maintain

ownership of the bus until the timer reaches zero (or has

finished the bus transfer). The timer is an 8-bit counter, with

the lower 4 bits hard-coded to 1111b. This means that the

timer value can only be incremented in units of 16 clocks.

3.2.4 32-Bit Data Operation

The DP83821 supports only 32-bit operation as a bus

master or target for transferring descriptor and packet data

information. At the rising edge of RSTN, the DP83821

samples the REQ64N pin and determines the bus to be 32-

bit capable. Since this pin must be tied high, it indicates the

bus is not 64-bit capable

3.2.5 32-Bit Addressing

The DP83821 supports only 32-bit addressing as a bus

master or target for transferring descriptor and packet data

information.

This

mode

must

enabled

through

configuration from EEPROM.

3.3 Bus Operation

3.3.1 Target Read

A Target Read operation starts with the system generating

FRAMEN, Address, and either an IO read (0010b) or

Memory Read (0110b) command. See Figure 3-4. If the

32-bit address on the address bus matches the IO address

range specified in CFGIOA:IOBASE (for I/O reads) or the

memory address range specified in CFGMA:MEMBASE

(for memory reads), the DP83821 will generate DEVSELN

2 clock cycles later (medium speed).

The system must tri-state the Address bus, and convert the

C/BEN bus to byte enables, after the address cycle. On the

2nd cycle after the assertion of DEVSELN, all 32-bits of

data and TRDYN will become valid. If IRDYN is asserted at

that time, TRDYN will be forced HIGH on the next clock for

1 cycle, and then tri-stated.

If FRAMEN is asserted beyond the assertion of IRDYN, the

DP83821 will still make data available as described above,

but will also issue a Disconnect. That is, it will assert the

STOPN signal with TRDYN. STOPN will remain asserted

until FRAMEN is detected as deasserted.

Byte 3Byte 2Byte 1Byte 0

24 23

16 15

8 7

(MSB)

(LSB)

C/BEN[3]

C/BEN[2]

C/BEN[1]

C/BEN[0]

Byte 0Byte 1Byte 2Byte 3

24 23

16 15

8 7

(LSB)

(MSB)

C/BEN[3]

C/BEN[2]

C/BEN[1]

C/BEN[0]

DP83821 Datasheet(PDF) 11 Page - National Semiconductor (TI)

DP83821 Datasheet(HTML) 11 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL