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DP83821 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP83821 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 86 page  © 2001 National Semiconductor Corporation www.national.com PRELIMINARY February 2001 DP83821 10/100/1000 Mb/s PCI Ethernet Network Interface Controller General Description DP83821 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high- performance adapter cards and mother boards. The DP83821 fully implements the V2.2 33 MHz, 32-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83821 can support full duplex 10/100/1000 Mb/s transmission and reception. Features — IEEE 802.3 Compliant, 33 Mhz, 32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet. — Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes) — BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a — Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change — GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices — Ten-Bit Interface (TBI) for support of 1000BASE-X — Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets — 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds — IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers — 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions. — Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns. — Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management. — Internal 8 KB Transmit and 32 KB Receive data FIFOs — Supports Jumbo packets — Serial EEPROM port with auto-load of configuration data from EEPROM at power-on — Flash/PROM interface for remote boot support — Full Duplex support for 10/100/1000 Mb/s data rates — 208-pin PQFP package — Low power CMOS design — 3.3V powered I/Os with 5V tolerant inputs — JTAG Boundary Scan supported System Diagram PCI B u s D P 8 3821 E E P R O M (o ptiona l) 10 /1 0 0 /1 000 M b /s PH Y B o ot R O M (o p tional) MII GM II |
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