PPC440GX-3RF800C datasheet(10/93 Pages) AMCC

10 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

PowerPC 440 Processor Core

The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, ISCSI, routers,

switches, printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded

architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

• Up to 800MHz operation

• PowerPC Book E architecture

• 32KB I-cache, 32KB D-cache

- UTLB Word Wide parity on data and tag address parity with exception force

• Three logical regions in D-cache: locked, transient, normal

• D-cache full line flush capability

• 41-bit virtual address, 36-bit (64GB) physical address

• Superscalar, out-of-order execution

• 7-stage pipeline

• 3 execution pipelines

• Dynamic branch prediction

• Memory management unit

- 64-entry, full associative, unified TLB with parity

- Separate instruction and data micro-TLBs

- Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

• Debug facilities

- Multiple instruction and data range breakpoints

- Data value compare

- Single step, branch, and trap events

- Non-invasive real-time trace interface

• 24 DSP instructions

- Single-cycle multiply and multiply-accumulate

- 32 x 32 integer multiply

- 16 x 16 -> 32-bit MAC

Internal Buses

The PowerPC 440GX features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip

Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores

such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to

the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for

passing status and control information between the processor core and the other on-chip cores.

Features include:

•PLB

- 128-bit implementation of the PLB architecture

- Separate and simultaneous read and write data paths

- 64-bit address

- Simultaneous control, address, and data phases

- Four levels of pipelining

- Byte enable capability supporting unaligned transfers

- 32- and 64-byte burst transfers

- 166MHz, maximum 5.2GB/s (simultaneous read and write)(200MHz for 800MHz Rev F parts)

- Processor:bus clock ratios of N:1 and N:2

PPC440GX-3RF800C Datasheet(PDF) 10 Page - Applied Micro Circuits Corporation

PPC440GX-3RF800C Datasheet(HTML) 10 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL