PPC440GX-3RF800C datasheet(53/93 Pages) AMCC

53 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

GMCCrS,

GMC1TxClk,

RTBI1TxClk

GMII: Carrier sense

RGMII: Transmit clock

RTBI: Transmit clock

I/O

3.3V tolerant

2.5V CMOS

GMCRefClk

GMII, RGMII, TBI and RTBI: Gigabit reference clock

3.3V tolerant

2.5V CMOS

GMCRxD0:3,

GMC0RxD0:3,

TBIRxD0:3,

RTBI0RxD0:3

GMII: Receive data

RGMII: Receive data

TBI: Receive data

RTBI: Receive data

3.3V tolerant

2.5V CMOS

GMCRxD4:7,

GMC1RxD0:3,

TBIRxD4:7,

RTBI1RxD0:3

GMII: Receive data

RGMII: Receive data

TBI: Receive data

RTBI: Receive data

3.3V tolerant

2.5V CMOS

GMCRxDV,

GMC0RxCtl,

TBIRxD8,

RTBI0RxD4

GMII: Receive data valid

RGMII: Receive control

TBI: Receive data

RTBI: Receive data

3.3V tolerant

2.5V CMOS

GMCRxEr,

GMC1RxCtl,

TBIRxD9,

RTBI1RxD4

GMII: Receive error

RGMII: Receive control

TBI: Receive data

RTBI: Receive data

I/O

3.3V tolerant

2.5V CMOS

GMCTxEn,

GMC0TxCtl,

TBITxD8,

RTBI0TxD4

GMII: Transmit data enable

RGMII: Transmit control

TBI: Transmit data

RTBI: Transmit data

3.3V tolerant

2.5V CMOS

GMCTxEr,

GMC1TxCtl,

TBITxD9,

RTBI1TxD4

GMII: Transmit error

RGMII: Transmit control

TBI: Transmit data

RTBI: Transmit data

3.3V tolerant

2.5V CMOS

GMCTxClk

TBIRxClk1

GMII: 10/100Mbps Transmit clock

TBI: Receive clock 1

I/O

3.3V LVTTL

External Slave Peripheral Interface

DMAAck0:3

Used by the PPC440GX to indicate that data transfers have

occurred.

3.3V tolerant

2.5V CMOS

DMAReq0:3

Used by slave peripherals to indicate they are prepared to transfer

data.

3.3V tolerant

2.5V CMOS

1, 5

EOT0:3/TC0:3

End Of Transfer/Terminal Count.

I/O

3.3V tolerant

2.5V CMOS

1, 5

PerAddr00:31

Peripheral address bus used by PPC440GX when not in external

master mode, otherwise used by external master.

Note: PerAddr00 is the most significant bit (msb) on this bus.

I/O

3.3V LVTTL

PerWBE0:3

External peripheral data bus byte enables.

I/O

3.3V LVTTL

1, 2

PerBLast

Used by either the peripheral controller, DMA controller, or

external master to indicates the last transfer of a memory access.

I/O

3.3V LVTTL

1, 4

PerCS0:7

External peripheral device select.

3.3V LVTTL

PerData00:31

Peripheral data bus used by PPC440GX when not in external

master mode, otherwise used by external master.

Note: PerData00 is the most significant bit (msb) on this bus.

I/O

3.3V LVTTL

Signal Functional Description (Sheet 4 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440GX-3RF800C Datasheet(PDF) 53 Page - Applied Micro Circuits Corporation

PPC440GX-3RF800C Datasheet(HTML) 53 Page - Applied Micro Circuits Corporation

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