PPC440GX-3RF800C datasheet(83/93 Pages) AMCC

83 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

DDR SDRAM Read Operation

The following examples of timing for DDR SDRAM read operations are based on the relationship between the

incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of

MemClkOut(0) relative to the PLB clock (TMD) is provided.

The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the

PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be

programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set

in RDCT. The delay of Read Clock relative to the PLB clock (TRD) shown below assumes the programmable Read

Clock delay is set to zero.

I/O Timing—DDR SDRAM TSD and THD

Notes:

1. TSD and THD are measured under worst case conditions.

2. The time values in the table include 1/4 of a cycle at the indicated clock speed.

3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values at 166MHz in the table

and add 1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.5 + 0.25TCYC).

Clock Speed (MHz)

Signal Names

Reference Signal

TSD (ns)

THD (ns)

166

MemData00:07, DM0

DQS0

1.240

1.224

166

MemData08:15, DM1

DQS1

1.236

1.188

166

MemData16:23, DM2

DQS2

1.223

1.224

166

MemData24:31, DM3

DQS3

1.221

1.185

166

MemData32:39, DM4

DQS4

1.238

1.230

166

MemData40:47, DM5

DQS5

1.286

1.175

166

MemData48:55, DM6

DQS6

1.234

1.214

166

MemData56:63, DM7

DQS7

1.257

1.154

166

ECC0:7, DM8

DQS8

1.237

1.243

200

MemData00:07, DM0

DQS0

0.916

0.542

200

MemData08:15, DM1

DQS1

1.018

0.522

200

MemData16:23, DM2

DQS2

1.017

0.527

200

MemData24:31, DM3

DQS3

0.951

0.532

200

MemData32:39, DM4

DQS4

1.030

0.533

200

MemData40:47, DM5

DQS5

1.014

0.536

200

MemData48:55, DM6

DQS6

0.994

0.534

200

MemData56:63, DM7

DQS7

0.994

0.546

200

ECC0:7, DM8

DQS8

1.000

0.532

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