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PPC440GX-3RF800C Datasheet(PDF) 89 Page - Applied Micro Circuits Corporation |
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PPC440GX-3RF800C Datasheet(HTML) 89 Page - Applied Micro Circuits Corporation |
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89 / 93 page ![]() 440GX – Power PC 440GX Embedded Processor AMCC 89 Revision 1.15 – August 30, 2007 Data Sheet Initialization The PPC440GX provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). Strapping While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default initial conditions prior to PPC440GX start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. They are used for strap functions only during reset. Following reset they are used for normal functions. The following table lists the strapping pins along with their functions and strapping options: Serial EEPROM During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of SysReset, if the bootstrap controller is enabled, the PPC440GX sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2, and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440GX Embedded Processor User’s Manual. Strapping Pin Assignments Function Option Ball Strapping V24 (UART0_DCD) V02 (UART0_DSR) L07 (GMC1TxEr) Serial device is disabled. Each of the four options (A– D) is a combination of boot source, boot-source width, and clock frequency specifications. Refer to the IIC Bootstrap Controller chapter in the PPC440GX Embedded Processor User’s Manual for details. A 000 B0 x 1 C 010 D 100 Serial device is enabled. The option being selected is the IIC0 slave address that will respond with strapping data. 0x54 1 0 1 0x50 1 1 1 |
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