PPC440GX-3RF800C datasheet(82/93 Pages) AMCC

82 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

I/O Timing—DDR SDRAM TSK, TSA, and THA

Notes:

1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).

2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and

subtract TSK maximum at 166MHz (0.75TCYC - TSKmax).

3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add

TSK minimum at 166MHz (0.25TCYC + TSKmin).

Clock Speed (MHz)

Signal Name

TSK (ns)

TSA (ns)

THA (ns)

Minimum

Maximum

Minimum

166

MemAddr00:12

0.184

0.592

3.908

1.684

166

BA0:1

0.439

0.683

3.817

1.939

166

BankSel0:3

0.249

0.779

3.721

1.749

166

ClkEn0:3

0.344

0.724

3.776

1.844

166

CAS

0.319

0.561

3.939

1.819

166

RAS

0.373

0.683

3.817

1.873

166

0.393

0.639

3.816

1.893

200

MemAddr00:12

-0.283

0.307

3.443

0.967

200

BA0:1

-0.286

0.353

3.397

0.964

200

BankSel0:3

-0.270

0.321

3.429

0.980

200

ClkEn0:3

-0.280

0.298

3.452

0.970

200

CAS

-0.270

0.294

3.456

0.980

200

RAS

-0.263

0.311

3.439

0.987

200

-0.280

0.288

3.462

0.970

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