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PPC440GX-3RF800C Datasheet(PDF) 72 Page - Applied Micro Circuits Corporation |
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PPC440GX-3RF800C Datasheet(HTML) 72 Page - Applied Micro Circuits Corporation |
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72 / 93 page ![]() 440GX – Power PC 440GX Embedded Processor 72 AMCC Revision 1.15 – August 30, 2007 Data Sheet Ethernet SMII Interface EMC0:1RxD 0.8 0.8 na na 5.1 6.8 EMCRefClk EMC2:3RxD 0.8 0.8 na na 5.1 6.8 EMCRefClk EMC0:1TxD na na 3.5 2 5.1 6.8 EMCRefClk EMC2:3TxD na na 3.5 2 5.1 6.8 EMCRefClk EMCRefClk na na na na na na 4, async Ethernet GMII Interface GMCRxClk na na na na na na 1, async GMCRxD0:7 2 0 na na 5.1 6.8 GMCRxClk GMCRxEr 2 0 na na 5.1 6.8 GMCRxClk GMCRxDV 2 0 na na 5.1 6.8 GMCRxClk GMCCrS na na 5.1 6.8 1, async GMCol na na 5.1 6.8 1, async GMCGTxClk na na na na na na 1, async GMCTxD0:7 na na 5.5 0.5 5.1 6.8 GMCGTxClk GMCTxEr na na 5.5 0.5 5.1 6.8 GMCGTxClk GMCTxEn na na 5.5 0.5 5.1 6.8 GMCGTxClk I/O Specifications—All Speeds (Sheet 3 of 7) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz. 3. The clock frequency for RMII operation is 50MHz ± 100ppm. 4. The clock frequency for SMII operation is 125MHz ± 100ppm. 5. These are DDR signals that can change on both the positive and negative clock transitions. Signal Input (ns) Output (ns) Output Current (mA) Clock Notes Setup Time (TIS min) Hold Time (TIH min) Valid Delay (TOV max) Hold Time (TOH min) I/O H (minimum) I/O L (minimum) |
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