STPM32 datasheet(46/89 Pages) STMICROELECTRONICS

46 / 89 page

Byte

Master-side transmitted data

Slave-side transmitted data

5 (optional)

Master CRC verification packet

Slave CRC verification packet

The above information is exchanged between master and slave in the same communication session, or

transaction. SPI master can issue a read-request and a write-request (optional).

The master initiates the communication sending the STPM3x a frame see Table 23 (read address - write address

- LS data byte - MS data byte - optional CRC).

Two command codes are provided:

•

Dummy read address 0xFF increments by one the internal read pointer

•

Dummy write address 0xFF specifies that no writing is requested (the two following incoming data frames

are ignored)

Upon the reception of a frame, the STPM3x replies to master data sending the 32-bit register addressed during

the previous communication session; during the first session the slave sends, by default, the 32-bit data stored

into the first (row 0) memory register. Data are organized in 8-bit packets so that the least significant byte is sent

first and the most significant byte is sent last.

A final 8-bit CRC packet is sent to master to verify no data corruption has occurred during the transmission from

slave to master. The CRC feature, enabled by default, can be controlled by a configuration bit into US_REG1

memory row (read address 0x24, write address 0x24).

If CRC bit in US_REG1 is cleared, the communication consists of 4 bytes only.

Write-requests are executed immediately after the transaction has completed, while read- requests are fulfilled at

the end of the next transaction only, because the sent read-address has just set the internal register pointer to

deliver data during the following transaction.

So, while one transaction is enough to write data into memory, at least two transactions are needed to read

selected data from memory.

Databytes are swapped with respect to the order of the byte, since during transmission, the 3rd byte sent to MOSI

line is the least-significant (LS) byte (bits [7:0]) and the 4th byte is the most-significant (MS) byte of the data to be

written (bits [15:8]).

On MISO line, the first data byte received is the least-significant (LS, bits [7:0]) and the last is the most-significant

(MS, bits [31:24]) of the record, as shown below.

Figure 48. Single communication time frame

Read Address

Write Address

LS Data [7:0]

MS Data [15:8]

CRC Byte

Data [7:0]

Data [15:8]

Data [23:16]

Data [31:24]

CRC Byte

MOSI

MISO

SCS

timeline

Data and configuration registers are organized into 32-bit rows in the internal memory, but can only be accessed

16-bit at a time for writing operations.

The address space is 70 rows wide, so there are 70 32-bit addressable elements for reading operations; since the

first 21 configuration registers are writable, there are 42 (= 21 x 2) 16-bit addressable elements for writing

operations.

STPM32, STPM33, STPM34

Communication protocol

DS10272 - Rev 13

page 46/89

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