STPM32 datasheet(47/89 Pages) STMICROELECTRONICS

47 / 89 page

Figure 49. Memory data organization

Read Address

Write Address

LS Data [7:0]

MS Data [15:8]

Data [7:0]

Data [15:8]

Data [23:16]

Data [31:24]

Data [7:0]

Data [15:8]

Data [23:16]

Data [31:24]

Data [7:0]

Data [15:8]

Data [23:16]

Data [31:24]

LS Data [7:0]

MS Data [15:8]

32 bits

16 bits

Two different codes are used for the read address space and write address space, which can be found in the

8.6.1

Synchronization and remote reset functionality

Data into read-only registers are updated internally by DSP with frequency: 7.8125 kHz (clock frequency

measure). Latching is used to sample the updated results into transmission latches. The transmission latches are

flip-flops holding the data in the communication interface.

Data latching can be implemented in three ways:

•

Using SYN and SCS pin

•

Writing the channel latch bits before each reading (S/W Latchx in DSP_CR3)

•

Writing auto-latch bit (S/W Auto Latch in DSP_CR3) to automatically latch data registers every clock

measure period (128 μs).

The remote reset can be performed in two ways:

•

Using SYN and SCS pin

•

Writing the reset bit (S/W reset in DSP_CR3).

SYN pin: latching, reset and global reset

Latching of internal memory registers can be carried out by producing pulses of a given width on SYN pin while

SCS line is high as depicted in Figure 50.

If a single pulse on SYN is detected, latch occurs.

If two consecutive pulses are detected, a reset of measurement registers occurs and the counters are reset, as

well.

If three consecutive pulses are detected, a global reset occurs, the configuration is also reset and the chip must

be initialized again.

Note:

To ensure a correct initialization of DSP, it is recommended to perform a global reset through three SYN pulses

at start up and before setting configuration bits.

Figure 50. Latching and reset through SYN pulses

SCS

SYN

timeline

Latch edges

Reset edge

Latch pulse width and other SPI timings are reported in Table 4.

STPM32, STPM33, STPM34

Communication protocol

DS10272 - Rev 13

page 47/89

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