STPM32 datasheet(36/89 Pages) STMICROELECTRONICS

36 / 89 page

If the voltage signal frequency is out of this range, PER_ERR status bit is set in DSP_SR1/2.

PER_ERR = 0: period in the range

PER_ERR = 1: period out of range

PER_ERR bit can be also set when a sag event is detected.

When PER_ERR bit is set, PHx_PERIOD[11:0] is not updated and keeps the previous correct value.

Setting the default line frequency through REF_FREQ bit in register DSP_CR3 speeds up the period calculation

algorithm convergence.

Phase-angle measurement

From the period information, the device calculates phase-delay between voltage and current for the fundamental

harmonic.

Cx_PHA[11:0] data for primary and secondary channel are located in DSP_REG17 and

DSP_REG19 respectively.

Phase-angle φ in degrees can be calculated from the register value as follows:

Equation 13

φ=Cx_PHA11:0

FClk

∙f∙360°

(13)

Resolution at 50 Hz is:

Equation 14

∆PℎaseAngle= 0x001125kHz∙50Hz∙360°=0.144°

(14)

When PER_ERR bit is set, Cx_PHA[11:0] is not updated and keeps the previous correct value.

8.4.10

Sag and swell detection

The device can detect and monitor the undervoltage (also called voltage dip or sag) and the overvoltage or

overcurrent events (swell).

A 4-bit event register stores every time that the sag or swell condition is verified.The event history is stored in

DSP_EV1 and DSP_EV2 registers as SAGx_EV[3:0], SWVx_EV[3:0] and SWCx_EV[3:0]. From the event

DSP_REG19.

To correctly detect the event, thresholds have to be set from DSP_CR5 to DSP_CR8 as explained below.

To clear event history and time registers, once the event has been detected, ClearSS bit in DSP_CR1, DSP_CR2

has to be set. This bit is reset automatically.

To avoid a race condition on digital counters, a time register CLRSS_TO[3:0] (ClearSS reset time) can be set to

extend the reset duration of ClearSS bit. LSB of this register is 8 μs.

Status bits are also available in case of sag and swell events in DSP_SR1 and DSP_SR2, they can give the

information about the sag/swell event start or end and generate an interrupt if masked in DSP_IRQ1 and

DSP_IRQ2 registers.

STPM32, STPM33, STPM34

Functional description of hardwired DSP

DS10272 - Rev 13

page 36/89

STPM32 Datasheet(PDF) 36 Page - STMicroelectronics

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