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STPM32 Datasheet(PDF) 24 Page - STMicroelectronics |
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STPM32 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 89 page  Figure 27. Clock feed for multiple devices CLKIN/XTAL2 XTAL1 CLKOUT/ZCR CLKIN/XTAL2 XTAL1 CLKOUT/ZCR 15pF 15pF 1MΩ CLKIN/XTAL2 XTAL1 CLKOUT/ZCR 8.2.4 Power-on-reset (POR) and enable (EN) The STPM3x contains a power-on-reset (POR) circuit which delays the startup of the digital domain about 750 μs. If VCC supply is less than 2.5 V the STPM3x goes to the inactive state, all functions are blocked asserting a reset condition. This is useful to assure the correct device operation during the power-up and power-down. POR sequence is illustrated in Figure 28: after the start of two LDOs and internal PowerOK signals are asserted, the analog block first and the digital block after start the processing. Figure 28. Power-on-reset sequence VDDA LDR 3.0V LDR 1.2V VDDD PowerOK_3.0V PowerOK_1.2V EN POR 16MHz Osc XTAL2 XTAL1 VCC OSC CLKIN The STPM3x also has an enable pin (EN) which works as follows: • EN is high: when the power is on and EN pin raises, the device is enabled and starts after POR procedure as above described. • EN is low: when the power is on and EN pin has a transition high to low, the device is disabled. It stops and the internal digital memory is deleted so a new initialization is needed when EN goes back to high. After POR, to ensure a correct initialization, it is necessary to perform a reset of DSP and communication peripherals through three SYN pulses (see Figure 29. Global startup reset) and a single SCS pulse, as shown in the figure below. SCS pulse can be performed before or after SYN pulses, but minimum startup time before reset (as indicated in Table 4) has to be respected. STPM32, STPM33, STPM34 Functional description of the analog part DS10272 - Rev 13 page 24/89 |
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