STPM32 datasheet(22/89 Pages) STMICROELECTRONICS

22 / 89 page

Figure 24. Analog front end internal scheme

IIPx

IINx

VIPx

VINx

2nd ord ΣΔ

modulator

2nd ordΣΔ

modulator

PLNA

GAINx[1:0]

DFE

bsV

bsC

PLNA uses the chopping technique to cancel the intrinsic offset of the amplifier.

A dedicated block generates chopper frequencies for voltage and current channels. The amplified signals are fed

to the 2nd order sigma-delta modulator.

The analog-to-digital conversion in the STPM3x is carried out using four 2nd order sigma-delta converters. A

pseudo-random block generates pseudo-random signals for voltage and current channels. These random signals

implement the dithering technique in order to de-correlate the output of the modulators and avoid accumulation

points on the frequency spectrum. The device performs A/D conversions of analog signals on four independent

channels in parallel.

Figure 25. Block diagram of the modulator

D/A

1st integrator

2nd integrator

comparator

input

Dithering

stream out

The sigma-delta modulators convert the input signals into a continuous serial stream of “1” and “0” at a rate

determined by the sampling clock. In the STPM3x, the oversampling clock is equal to 4 MHz.

1-bit DAC in the feedback loop is driven by the serial data stream. DAC output is subtracted from the input signal

and from the integrated error. If the loop gain is high enough, the average value of DAC output (and therefore the

bitstream) can approach to the input signal level. When a large number of samples are averaged, a very precise

value of the analog signal is obtained. This average is described in DSP section.

STPM32, STPM33, STPM34

Functional description of the analog part

DS10272 - Rev 13

page 22/89

STPM32 Datasheet(PDF) 22 Page - STMicroelectronics