STPM32 datasheet(48/89 Pages) STMICROELECTRONICS

48 / 89 page

Figure 51. Latching through SYN pulses

MOSI

MISO

SCS

timeline

SYN

active edge

inactive edges

Software latch

Writing S/W Latchx configuration bits of DSP_CR3 register can latch data into transmission latches. These two

bits latch channel 1 and channel 2 data registers respectively; once set, they latch data and are automatically

reset. By setting S/W Auto Latch bit, latching is performed automatically at the rate of sampling clock, so data

latching, before each reading request, is no longer necessary.

Software reset

Writing SW Reset configuration bit in DSP_CR3 brings the configuration registers to their default values. Data

registers are not reset. This bit is automatically cleared after this action.

8.6.2

SPI peripheral

The device implements a full-duplex communication protocol using MISO, MOSI ports for data exchange, SCL for

clock port, SCS port for data exchange activation and SYN for internal register data latching and resetting, when

no data activation is set (SCS in off-state). Latching and resetting can also be performed by setting the related

bits in DSP_CR3 register.

With reference to the general SPI protocol, the peripheral is configured to work according to the following settings:

cpol = 1, cpha = 1.

SPI control register

US_REG1 register contains 16-bits with all the configuration parameters of t SPI and UART interfaces of the

STPM3x. Table 24 describes SPI related bits:

Table 24. SPI control register

Bit position in row

Name

Description

Default value

LSBfirst

Little(1) or big(0) - endian for bit transmission in data-

byte

CRCenable

Enable/disable CRC feature

[7:0]

CRCPolynomial

Polynomial used to validate transmitted and received

data

0x07

LSBfirst: endianness of data-byte transmission and reception

CRCenable: enables the optional CRC feature

CRCPolynomial: default polynomial used is 0x07 (x8+x2+x+1)

SPI timings

Any single transaction timing follows the scheme in Figure 7.

For consecutive writing transactions, a minimum time interval of 4μs has to be taken into account in order to avoid

overrun issues.

For latch and consecutive read transactions a minimum time interval of 4 μs has to be taken into account in order

to avoid overrun issues.

STPM32, STPM33, STPM34

Communication protocol

DS10272 - Rev 13

page 48/89

STPM32 Datasheet(PDF) 48 Page - STMicroelectronics

STPM32 Datasheet(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL