STPM32 datasheet(64/89 Pages) STMICROELECTRONICS

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Table 43. Row 2, DSP control register 3 (DSP_CR3)

Bit

Internal signal

Description

Default

[13:0]

TIME_VALUE

Time counter threshold for voltage sag detection

0x4E0

[15:14]

ZCR_SEL

Selection bit for ZCR/CLK pin, (output depends on ZCR/CLK enable

bit):

ZCR_SEL[1:0]: 00, 01, 10, 11

ZCR: V1, C1, V2, C2

CLK: 7.8125 kHz, 4 MHz, 4 MHz, 50% duty cycle, 16 MHz

0x0

ZCR_EN

ZCR/CLK pin output:

0: CLK

1: ZCR

0x0

[18:17]

TMP_TOL

Selection bits for tamper tolerance:

TMP_TOL[1:0]: 00, 01, 10, 11

Tolerance: 12.5%, 8.33%, 6.25%, 3.125%

0x0

TMP_EN

Enable tampering feature:

0: tamper disable

1: tamper enable

0x0

S/W reset

SW reset brings the configuration registers to default This bit is set to

zero after this action automatically

S/W latch1

Primary channel measurement register latch

This bit is set to zero after this action automatically

S/W latch2

Secondary channel measurement register latch

This bit is set to zero after this action automatically

S/WAuto Latch

Automatic measurement register latch at 7.8125 kHz

LED1OFF

LED1 pin output disable

0: LED1 output on

1: LED1 output disabled

When the LED output is disabled the pin is set at low-state

LED2OFF

LED2 pin output disable

0: LED2 output on

1: LED2 output disabled

When the LED output is disabled the pin is set at low-state

EN_CUM

Cumulative energy calculation

0: cumulative is the sum of channel energies

1: total is the difference of energies

REF_FREQ

Reference line frequency:

0: 50 Hz

1: 60 Hz

[31:28]

Reserved

Table 44. Row 3, DSP control register 4 (DSP_CR4)

Bit

Internal signal

Description

Default

[9:0]

PHC2

Secondary current channel phase compensation register

0x0

[11:10]

PHV2

Secondary voltage channel phase compensation register

0x0

STPM32, STPM33, STPM34

Configuration register

DS10272 - Rev 13

page 64/89

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