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ORCA ORSPI4 Data Sheet

Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

SPIA_TX64_ADDR_0[2:0]

FPGA

→ Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum

of eight partitions. When operating in 64-bit mode, each partition will be 2x

the depth of the corresponding partition in 32-bit mode. More than one port

can be conﬁgured to share a virtual FIFO partition.

SPIA_TX64_DATA_0[63:0]

FPGA

→ Core User Write data. Two writes are required in order to complete an entire 128-

bit line. All writes must occur in two write bursts, unless an EOP occurs.

SPIA_TX64_BE_0[7:0]

FPGA

→ Core Byte enables indicating which bytes within the 64-bit word are valid.

Bit[7]-Byte enable for SPIA_TX64_DATA_0[63:56]

Bit[6]-Byte enable for SPIA_TX64_DATA_0[55:48]

Bit[5]-Byte enable for SPIA_TX64_DATA_0[47:40]

Bit[4]-Byte enable for SPIA_TX64_DATA_0[39:32]

Bit[3]-Byte enable for SPIA_TX64_DATA_0[31:24]

Bit[2]-Byte enable for SPIA_TX64_DATA_0[23:16]

Bit[1]-Byte enable for SPIA_TX64_DATA_0[15:8]

Bit[0]-Byte enable for SPIA_TX64_DATA_0[7:0]

If no BE bits are asserted for a particular location within the DPRAM, data

will be dropped and no write to the DPRAM will occur.

According to the SPI-4.2 speciﬁcation, the BE bits must be asserted for all

but the last transfer, where an End of Packet or Error may occur. The valid

combinations of BE are as follows:

BE[7:0] = 11111111--indicates all eight bytes contain valid user data. If an

EOP is present, it resides within the eighth byte.

BE[7:0] = 11111110--indicates seven bytes are valid. EOP occurs in seventh

Byte.

BE[7:0] = 11111100--indicates six bytes are valid. EOP occurs in sixth Byte.

BE[7:0] = 11111000--indicates ﬁve byte is valid. EOP occurs in ﬁfth Byte.

BE[7:0] = 11110000--indicates four bytes are valid. EOP occurs in fourth

Byte.

BE[7:0] = 11100000--indicates three bytes are valid. EOP occurs in third

Byte.

BE[7:0] = 11000000--indicates two bytes are valid. EOP occurs in second Byte.

BE[7:0] = 10000000--indicates one byte is valid. EOP occurs in ﬁrst Byte.

SPIA_TX64_SOP_0

FPGA

→ Core Start of Packet indicator. A '1' indicates the start of packet for a particular

port. When operating in 64-bit mode, the SOP indicator must be asserted

coincident with the ﬁrst write per address line within the FIFO partition.

SPIA_TX64_EOP_0

FPGA

→ Core End of Packet indicator. A '1' indicates the end of packet for a particular

port. The EOP may be asserted on either write per address line within the

FIFO partition.

When an EOP is detected by the DPRAM Write Pointer Logic, the address

pointer will be automatically incremented to the next location within the

FIFO partition range.

SPIA_TX64_ERR_0

FPGA

→ Core Packet error indication. A '1' indicates an error has occurred for the current

packet being transmitted. The ERR signal must be asserted coincident with

the EOP signal.

SPIA_TX64_WE_0

FPGA

→ Core Write Enable. A logic '1' causes data on the SPIA_TX64_DATA_0[63:0] bus

to be captured for a write to the DPRAM.

SPIA_TX64_PORT_0[7:0]

FPGA

→ Core SPI4 port indicator, used to associate the current transmit data with a par-

ticular port number.

SPIA_TX64_WD_CNT_RST_

FPGA

→ Core Line Write Termination indicator. This signal causes the FIFO write address

pointer within the embedded core to increment to the next address location

for the addressed partition. This signal can be used for custom applications

as well as for diagnostic test functions.

Note: For SPIB replace A with B

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