ORSPI4 datasheet(17/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external

clocks.

• Four-channel HSI functions provide 2.96 Gbits/s serial user data interface per channel (8b/10b encoding and

decoding) for a total chip bandwidth of > 10 Gbits/s (full duplex).

• SERDES have low-power CML buffers and support 1.5 V or 1.8 V I/Os. This allows use of the SERDES with opti-

cal transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4.

• Powerdown option of SERDES HSI receiver or transmitter is on a per-channel basis.

• Automatic lock to reference clock in the absence of valid receive data.

• High-speed and low-speed loopback test modes.

• No external components required for clock recovery and frequency synthesis.

• Built-in boundary scan (

IEEE

® 1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES

interface.

• FIFOs can align incoming data either across groups of four channels or groups of two channels. Alignment is

done either using comma characters or by using the /A/ character in XAUI mode. Optional ability to bypass the

alignment FIFOs for asynchronous operation between channels (Each channel includes its own clock and frame

pulse or comma detect).

ORSPI4 FPGA Logic Overview

The following sections provide a brief overview of the main architectural features of the ORSPI4 FPGA logic. For

more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the

“Products” folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA

Data Sheet provides detailed information required for designing with the ORSPI4 device. Topics covered in the

ORCA Series 4 Data Sheet include:

• FPGA Logic Architecture

• FPGA Routing Resources

• FPGA Clock Routing Resources

• FPGA Programmable Input/Output Cells (PICs)

• FPGA Embedded Block RAM (EBR)

• Microprocessor Interface (MPI)

• Phase-Locked Loops (PLLs)

• Electrical Characteristics

• FPGA Timing Characteristics

• Power-up

• Conﬁguration

ORCA Series 4 FPGA Logic Overview

The

ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It

includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed

with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce

logic requirements and increase system speed.

ORCA Series 4 devices contain many new patented enhance-

ments and are offered in a variety of packages and speed grades.

ORSPI4 Datasheet(PDF) 17 Page - Lattice Semiconductor

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