ORSPI4 datasheet(68/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

ORSPI4 SPI4 Receive Path Functional Description

This section describes the receive section of the SPI4 interface. Although there will be two SPI4 compliant inter-

faces within the FPSC, this section describes a single interface. The other interface is a duplicate and therefore

needs no additional technical description.

ORSPI4 Receive Features

The Receive SPI4 interface supports the following features:

• 10 Gbits/s data throughput.

• Four dual-port memory banks supporting buffering for up to 32 ports. If support for more than 32 ports is needed,

then the dual-port memories can be used for clock domain crossing purposes and data can be buffered in an

external memory.

• Port Status Sequencer (PSS), including Receive Calendar (main and shadow), will support up to 256 ports, the

maximum number of ports supported by the SPI4 standard.

• 32, 64 and 128-bit data width aggregation modes at the user (core/FPGA) interface.

• Programmable main and shadow calendar table. All calendar conﬁguration parameters speciﬁed in the SPI4

standard such as CALENDAR_LEN, CALENDAR_M are supported.

• Optional dynamic alignment of receive data at the high-speed SPI4 interface. Dynamic alignment is required at

rates > 700 Mbits/s (350 MHz).

The SPI4 receive logic enables users to read incoming port data using a variety of interfaces and associated clock

domain options. It uses Dual Port RAMs (DPRAM) for temporary storage and clock domain crossing. Data is

received in SPI4 format as LVDS signals at the receive interface. The data is written into DPRAM as received and

read from the DPRAMs as requested by the FPGA logic. FIFO status is transmitted from the Receive Status inter-

face according to a pre-conﬁgured polling sequence contained within the Receive Calendar. Data is formatted into

the SPI4 Receive Status format and sent to the physical links as either LVDS or LVTTL signals.

There are also several other features incorporated into the embedded core such as parallel loopback and far end

loopback to assist in debugging and statistic gathering. These features, and the SPI4 data formats and initialization

procedures are documented in separate sections since they involve both the transmit and receive paths.

The major blocks associated with the ORSPI4 receiver are:

• SPI4 Receive Logic - Data

– SPI4 Receive Data Input (RDI) block

– SPI4 Receive Data Protocol (RDP) logic

• Data Formatter

• Address Map

• DPRAM Banks

• Port Status Sequencer Logic (PSS)

• SPI4 Receive Logic - Status

– SPI4 Receive Status Protocol (RSP) logic

– SPI4 Receive Status Output (RSO) block

ORSPI4 Datasheet(PDF) 68 Page - Lattice Semiconductor