ORSPI4 datasheet(7/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

• For low speed data, static alignment can be selected through a programmable control bit

– Speeds up to 350 MHz DDR (700 Mbits/s throughput)

– Dynamic alignment is bypassed and disabled to save power in static alignment mode.

– Programmable on-edge or on-center clock/data relationship option at receiver.

– Programmable clock delay

• Single-link and multi-link operation.

• SPI4 transmit data protocol support logic

– Combines the data and control words from the transmit FIFO (DPRAMs) into the SPI4 format

– Performs DIP-4 calculation over data and control words on the TX side and inserts into the payload control

word

• Handles all credit calculations based on the status information automatically

• Provides optional signals to FPGA interface logic for ﬂow control:

– Current transmit Port ID (Calendar Port or user speciﬁed port # per calendar port)

– Current BURST_VAL Parameter for that Port

– Status from that Port

• Embedded Calendar-based port polling sequence mechanism and bandwidth allocation for all 256 ports

– Programmable transmit and receive calendar tables support up to 256 ports

• Two calendars are supported in each direction

– Main Calendar (1K deep)

– Shadow Calendar (also 1K deep). User can reconﬁgure second calendar while operating off main calendar,

and then switch on the next cycle to allow hitless operation

– All calendar conﬁguration parameters speciﬁed in the standard (CALENDAR_LEN, CALENDAR_M, etc.) are

supported

• Transmit and Receive Status FIFOs provided to store ﬂow control information for up to 256 ports.

– Performs Status frame creation

– DIP-2 odd parity calculated over the status frames

– Supports either quarter-rate LVDS or LVTTL status channels

• Support for various options for ﬂow control status creation, selectable per port:

– Based on DPRAM FIFO ﬁll levels

– Based on status from FPGA interface per port

– Both of the above

• Dual-port RAM interface to the FPGA supports ﬂexible data widths for both the receive and transmit FPGA/core

interfaces.

– Scalable data bus enables users to conﬁgure TX interface for their respective port bandwidth requirements

– A total of 4 DPRAM banks where each of the DPRAMs can be logically partitioned into 1, 2, 4, or 8 virtual

FIFOs

– Used for temporary storage and clock domain crossing

– Can be conﬁgured to provide 32-, 64-, 128-bit data bus interfaces from the FPGA (plus accompanying con-

trol signals)

– 32-bit mode: Four banks are separate and accessed independently

– 64-bit mode: Banks 0 & 1 become a single aggregation and Banks 2 & 3 become a single aggregation

– 128-bit mode: All four banks become a single aggregation

– Mixed mode: One 64-bit (two banks become a single aggregation) and two banks are separate and

accessed independently

• Training pattern generation

– User controlled “alpha” repetitions of training pattern in TX_DATA_MAX_T intervals

– Automatic generation of training pattern during loss of synchronization

ORSPI4 Datasheet(PDF) 7 Page - Lattice Semiconductor

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