ORSPI4 datasheet(41/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 12 shows 32-bit write timing using fast back-to-back transfers.

Figure 12. 32-Bit Write Protocol Using Fast Back-to-Back Transfers

During clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM

the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and

control signals. In the ﬁgure, this is the start of a packet, so the SOP signal is also asserted. Data is presented to

the interface, as well as the Byte Enable (BE) and Port ID signals. The Port ID is used to identify the PORT_ID ﬁeld

within the SPI4 control word. The BE vector is used to qualify which Bytes on the SPI4 transmit link are valid data.

During clock cycle 4, the FPGA has completed writing an entire 128-bit line to the addressed DPRAM partition and

begins an access to another partition commencing with clock cycle 5. Since there was no EOP presented during

clock cycle 4, Port 3 must be revisited later with the remaining packet data and required EOP. The internal DPRAM

write is automatically incremented at the end of clock cycle 4 as well. During clock cycle 5, Port 7 is addressed as

the destination partition for the next 128-bit line burst sequence. During clock cycle 8, the BE bits are set to 0x8,

indicating only one of the four Bytes contain valid packet data. The EOP signal is also asserted during clock cycle 8

indicating the end of packet for the currently active Port 7.

Asserting the EOP signal causes the internal logic to terminate writes to the current Port, as well as automatically

incrementing to the next address for the FIFO partition.

During clock cycle 10, the FPGA returns to Port 3, completing the packet with two 32-bit bursts, and asserting the

EOP during the latter write cycle. All BE bits set to a logic ‘1’ during the second write indicates all four bytes of the

write are valid.

As shown, data may be written to different Ports, in a fast back-to-back fashion, without any reduction in data

throughput.

Some points to note are:

• According the SPI4 speciﬁcation, the smallest packet that may be transmitted across the Transmit SPI4 link con-

sists of a single 16-Byte transfer. This means a single occurrence of SOP and EOP may occur within any

DPRAM location.

• According to the SPI4 speciﬁcation, only a single Port's data may occur within a 16-Byte cycle. As a consequence,

data from a single Port is permitted to be written to any single 128-bit location within the DPRAM partitions.

SPI_TX32_CLK

SPI_TX32_WD_CNT_RST

SPI_TX32_ADDR[2:0]

SPI_TX32_WE

SPI_TX32_DATA[31:0]

SPI_TX32_SOP

SPI_TX32_EOP

SPI_TX32_PORT[7:0]

SPI_TX32_BE[3:0]

Internal DPRAM Write Ptr.

Addr 'm'

Addr 'n'

Addr 'n+1'

'm+1'

NOTE: SPIB is identical to SPIA

Port 3

Port 7

Port 3

0xF

0x8

0xF

Partition Addr 'k'

Addr 'k+1'

Addr 'k'

ORSPI4 Datasheet(PDF) 41 Page - Lattice Semiconductor

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