ORSPI4 datasheet(59/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

2. It is recommended that BURST_VAL for all ports be set to the same value equal to (data_burst_value/16). For

example, for a data burst requirement of 64 bytes, all port BURST_VAL should be set to 4. For a data burst require-

ment of 128 bytes, all port BURST_VAL should be set to 8. A maximum BURST_VAL of 15 will support a data burst

of 240 bytes. Having a common BURST_VAL for all ports simpliﬁes design of the sequencer needed to keep all

transmit ports ﬁlled sufﬁciently at all times for data bursts. With all port BURST_VAL the same, relative port band-

width can be set by loading the Transmit Calendar appropriately.

3. Set TX_FIFO_THRESHOLD_L (address 30945, bits [0:2] for SPIA, address 30A45, bits [0:2] for SPIB) to [inte-

ger(BURST_VAL/4) + 1]. For example, if BURST_VAL = 10, TX_FIFO_THRESHOLD_L should be set to 3.

4. Set MAXBURST1 and MAXBURST2 to integer multiples of BURST_VAL that are at least 2 times BURST_VAL.

For example, if BURST_VAL = 4, then MAXBURST1 could be set to 12 and MAXBURST2 could be set to 8. To

optimize a port for minimum bursts it is best to set MAXBURST1 and MAXBURST2 to as high a value as possible.

The reason for this is as follows.

Whenever the transmitter detects a SATIFIED status condition when polling a port, that port’s credit ﬁeld (stored in

the Port Descriptor Memory) is automatically decremented by BURST_VAL. If the credit ﬁeld ever drops below

BURST_VAL, the port poll will terminate, reducing the available time to ﬁll the transmit FIFOs for data bursts.

Therefore, it is recommended that the SPI[A,B]_k_STAT signal from the core be monitored and writing be sus-

pended to any port whose receive FIFO is SATISFIED. Writing to that port can commence once HUNGRY or

STARVING appears at the SPI[A,B]_k_STAT because this will guarantee that the credit ﬁeld for the port has been

updated to a value greater than BURST_VAL. Maximizing the values of MAXBURST1 and MAXBURST2 gives the

greatest time between credit update and potential decrement below BURST_VAL (which will eventually happen if

enough SATISFIED status conditions occur). This in turn simpliﬁes the design of a transmit FIFO data write state

machine.

5. In order to ensure that a full BURST_VAL block of data is always available when a port is serviced, it is neces-

sary to synchronize the writing of data to each port’s transmit FIFO to the transmitter’s FIFO read sequence. This

can be done by monitoring the PORT_ID of the currently serviced SPI4 port (SPI[A,B]_k_PORT_ID). Figure 21,

Figure 22, and Figure 23 show write sequencing that would result in sufﬁciently full transmit FIFOs for full data

bursts at all times (except for end-of-packet) for 32-bit, 64-bit, and 128-bit aggregation modes respectively. The ﬁg-

ures illustrate the most stringent polling sequencing that would still allow consistently full data bursts. For example,

the minimum required gap between polls of the same port is determined by the aggregation mode chosen. Longer

gaps between epeated port polling will result in more ﬂexibility in timing the transmit FIFO writes. The examples in

Figure 21, Figure 22, and Figure 23 illustrate a BURST_VAL of 4, but are extendable to BURST_VAL values from 2

to 15. Note that BURST_VAL for each port is available on SPI[A,B]_k_BURST_VAL. This may be useful in cases

where BURST_VAL has not been set to the same value for each port.

ORSPI4 Datasheet(PDF) 59 Page - Lattice Semiconductor