ORSPI4 datasheet(53/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

• AMA - This user conﬁgurable ﬁeld consisting of a DPRAM BANK_ID (left-most two bits) and a DPRAM

PARTITION_ID, indicates to the AMA (AMA_ID) which physical DPRAM partition address to poll for port servic-

ing. After reset, this ﬁeld defaults to a value of 5'h00.

• M - Indicates whether the programmed Port_ID or the SEQ_PORT_NUM contained within the Calendar

Sequence Table should be broadcast to the FPGA. This is performed on a per port basis, providing a mapping

function between proprietary FPGA port mapping and the SPI4 Transmit Calendar port number. EX: SPI4 Port

Number 138 maps to FPGA interface Device #7, Port #17. When the 'M'- bit is set to a logic one, the pro-

grammed Port_ID (i.e. 138) is broadcast to the FPGA for the port being serviced; when set to a logic zero, the

Port number from the Transmit Calendar is sent to the FPGA for that particular port. After reset, this ﬁeld should

default to a value of 1'b0.

• Credits - Indicates the number of bursts the port is permitted to transmit across the SPI4 link between status

updates, for that particular port. This ﬁeld is updated with calculated credit values after the port is serviced.

Whenever the receive status from the TSP block presents a port status value of 2'b11, the Credit ﬁeld for the

indexed port is to be cleared to a value of 10'h000. This disables the port. The user may conﬁgure an initial value

for each enable port. After reset, this ﬁeld is to default to a value of 10'h000. This ﬁeld should not be altered after

the Transmit Calendar is placed in operation.

• MB_EN - This user-conﬁgurable register indicates whether the associated port supports MAX_BURST parame-

ters as deﬁned within the SPI4 speciﬁcation. The Transmit Calendar supports a single TX_MAX_BURST1 and a

single TX_MAX_BURST2 value. Logic one indicates that the conﬁgured port supports MAX_BURST. After reset,

this ﬁeld is to default to a value of 1'b0. This is conﬁgurable on a per-port basis.

• STAT - Contains Transmit FIFO status from the TSP block. Used in conjunction with the MB_EN ﬁeld to update

the Credit ﬁeld for the indexed port. Also sent to the FPGA for status monitoring. After reset this ﬁeld is set to a

value of 2'h3, indicating the port is disabled.

Status Update Logic

Transmit status is received from the TSP block (described later). Both the port number and associated status of the

port is sent to the Status Update Logic. This block ensures that the status for each port, as it is received, is updated

correctly. The status is received according to the programmed far-end Calendar, and will generally be received

asynchronously (relative to port servicing) to the local Transmit Calendar polling.

By providing the BURST_VAL, Stat, and Port_ID value to the FPGA, application logic can maintain the required

data bandwidth it needs to source, in order to keep the respective FIFO partition from over/under-ﬂowing. These

signals can also be used in conjunction with FPGA control logic to oversee the operation of the Memory Controller

for accessing the Transmit SPI4 port data.

Transmit Status Input (TSI) Block

The Transmit Status Input (TSI) block provides the interface to the SPI4 Transmit Status Signals. These signals can

be either LVDS or LVCMOS input buffers. This is selected using the SPI4_STATUS_IO_SEL register setting. The

Status interface supports quarter-rate mode only, as deﬁned within the SPI4 speciﬁcation. The user has the option

to use the status input signals either in phase with status input clock, or out of phase with the status input clock, by

optionally inverting the input clock signal on-chip. Setting SPI_SATM_A and SPI_SATM_B registers to a “1” will

cause them to be in phase, setting to a “0” will cause them to be out of phase.

The TSI block receives transmit status and provides both the status information and a derived clock to the TSP

block.

Transmit Status Protocol (TSP) Block

The Transmit Status Protocol (TSP) block receives status from the TSI block and uses the user-conﬁgured transmit

calendar to associate the current received status with a port. This block performs FIFO status decoding, buffering

and DIP-2 calculations. As deﬁned within the SPI4 speciﬁcation, if DIP-2 errors occur, it sends an error ﬂag to the

TDP block for processing. The TSP provides port status information to the Transmit Calendar logic along with the

associated port number. The Calendar logic then updates the appropriate Port STAT ﬁeld. The TSP block also sup-

ports Hitless Bandwidth Provisioning as deﬁned within Appendix G of the SPI4 speciﬁcation.

ORSPI4 Datasheet(PDF) 53 Page - Lattice Semiconductor

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