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ORCA ORSPI4 Data Sheet

nally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for con-

ﬁguring FPGAs.

The RAM is loaded by using one of several conﬁguration modes. Supporting the traditional master/slave serial,

master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface

and Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and

partial reconﬁguration are also permitted.

Other conﬁguration options include the initialization of the embedded-block RAM memories and FPSC memory, as

well as system bus options and bit stream error checking. Programming and readback through the JTAG

(IEEE

1149.2

) port is also available, meeting In-System Programming (ISP) standards (IEEE 1532 Draft).

FPSC Conﬁguration

Conﬁguration of the ORSPI4 occurs in two stages: FPGA bit-stream conﬁguration and embedded core setup.

Prior to becoming operational, the FPGA goes through a sequence of states, including power-up, initialization, con-

ﬁguration, start-up, and operation. The FPGA logic is conﬁgured by standard FPGA bit-stream conﬁguration means

as discussed in the

ORCA Series 4 FPGA data sheet.

After the FPGA conﬁguration is complete, the options for the embedded core are set based on the contents of reg-

isters that are accessed through the FPGA system bus. The system bus itself can be driven by an external

Pow-

erPC compliant microprocessor via the MPI block or via a user master interface in FPGA logic. A simple IP block

that drives the system by using the user register interface and very little FPGA logic is available in the

MPI/System

Bus Technical Note (TN-1017). This IP block sets up the embedded core via a state machine and allows the

ORSPI4 to work in an independent system without an external microprocessor interface.

ORSPI4 Package Options

The ORSPI4 FPSC is available in two package options: a 1036 ftSBGA and a 1156 fpBGA. The 1036 pin package

provides an OR4E06 FPGA array (16,192 LEs, 148 Kbits of Embedded Block RAM), 498 FPGA user I/Os, two

SPI4 interfaces (or one SPI4 interface and a quad high-speed SERDES interface), and a high-speed QDRII SRAM

Controller. The 1156 pin package provides an OR4E06 FPGA array (16,192 LEs, 148 Kbits of Embedded Block

RAM), 356 FPGA user I/Os, two SPI4 interfaces (SERDES interface not available on this package), and a high-

speed QDRII SRAM Controller.

Additional Information

Contact your local Lattice representative for additional information regarding the

ORCA Series 4 FPGA devices, or

visit our website at: http://www.latticesemi.com/orca

Links to Specs and Standards

Optical Internetworking Forum – OIF-SPI4-02.0 - www.oiforum.com

Fibre Channel Physical and Signaling Interface – FC-PH ANSI X3.230-1994 - www.t11.org

10 Gigabit Ethernet – IEEE P802.3ae - www.ieee.org

18Mb QDR-II SRAM 2-word burst – MT54W512H36B - www.cypress.com/products/micron/micron.cfm

18Mb QDR-II SRAM 4-word burst – MT54W512H36B - www.cypress.com/products/micron/micron.cfm

36Mb QDR-II SRAM 2-word burst – KTR323682M - www.samsung.com/Products/Semiconductor/SRAM/index.htm

36Mb QDR-II SRAM 4-word burst – KTR323684M - www.samsung.com/Products/Semiconductor/SRAM/index.htm

ORSPI4 Datasheet(PDF) 23 Page - Lattice Semiconductor

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