ORSPI4 datasheet(54/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Transmit Calendar Operation

This section gives a description of how the Transmit Calendar operates, in order to assist users in understanding

how to conﬁgure the TX SPI4 programmable Calendar and conﬁguration registers to ﬁt their application. Figure 18

and Figure 19 will be used as reference. The Transmit Calendar logic is synchronous to TREFCLK for it’s internal

operations.

The Transmit Calendar logic uses an indirect addressing scheme to acquire port sequence information. This

enables the user to conﬁgure the Calendar easily, while minimizing the amount of information that needs to be pro-

grammed within the Calendar table. Indirect addressing also enables users to conﬁgure the entire Port Descriptor

Memory at initialization time, without having to actually enable all the entries. The user has access to modify port

information within the PDM at any time, whereas the Calendar(s) can only be updated while it is not in service.

The Transmit Calendar sequentially runs through all the user-enabled port entries within the 1K memory. The Cal-

endar rolls over to the ﬁrst entry whenever the user-conﬁgured maximum Calendar length is reached. The time

between polling the same port is a function of the several factors, including user-conﬁgured BURST_VAL per port,

and whether the TX_BURST_TERMINATION is enabled (set to LOGIC “1”).

• The user must conﬁgure the TX_CAL_LEN_MAIN to indicate the number of valid entries to sequence through in

the Main Calendar. Not all applications require 1023 locations to be polled.

• If the Shadow Calendar is to be used, the user must conﬁgure the TX_CAL_LEN_SHD to indicate the number of

valid entries to sequence in the Shadow Calendar. The Shadow Calendar is independent of the Main Calendar,

and may have a different number of entries.

• The user must either enable TX_BURST_TERMINATION or leave it disabled. By default it is disabled.

When a port is indexed within the Calendar, the indexed vector serves as the address to the Port Descriptor Mem-

ory, to fetch all the necessary information to service the selected port. The Port Descriptor Memory (PDM) provides

256 entries; one for each possible SPI4 port. The PDM contains all the port servicing control information. When a

port is indexed via the Calendar, the Calendar pointer is incremented to the next location, serving as a pseudo

prefetch in case TX_BURST_TERMINATION is enabled. Every time a Port is indexed in the PDM, an internal

counter loads BURST_VAL and begins decrementing. Upon nulling out, the next Calendar entry is used to index

the PDM to fetch the next port to be serviced. Again, the Calendar advances to the next enabled location. As

deﬁned within the SPI4 speciﬁcation, BURST_VAL indicates the number of 16-Byte cycles a port may be serviced

before segmentation must occur. Using BURST_VAL, the Transmit Calendar can maintain constant Port servicing

from the Dual Port memories.

• The user must conﬁgure a BURST_VAL value for each enabled SPI4 port. The PDM contains 256 locations, i.e.

one for each possible SPI4 port.

The Transmit Calendar broadcasts the AMA_ID and BURST_VAL vectors, fetched from the PDM, to the AMA

block. The AMA will use the ID value to address the physical entry of the port that is to be serviced. Note the

AMA_ID value is the physical address of the DPRAM and is made up of two user-conﬁgurable ﬁelds, the

PARTITION_ID and BANK_ID.

• The DPRAMs consist of 4 banks, and each may be partitioned into a maximum of 8 virtual FIFOs each. The user

must conﬁgure both the PARTITION_ID[2:0] and BANK_ID[1:0] ﬁelds for each enabled port within the PDM. The

PARTITION_ID vector is identical to the SPIA_TX32_ADDR_0[2:0]. The user conﬁgures the same partition

address for a particular port that is used as the address on transmit DPRAM write interface. The BANK_ID vector

is simply derived from the physical interface used at the FPGA/embedded core interface, as shown below.

– 32-bit mode

→ [00,01,10,11], providing up to 4 interfaces

– 64-bit mode

→ [00, 01], providing up to 2 interfaces

– 128-bit mode

→ [00], providing a single interface

For all combinations of aggregation, the values given above apply.

• More than one port can be mapped to the same partition. Simply program the same PARTITION_ID and

BANK_ID values in all the PDM port entries that share the same partition.

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