ORSPI4 datasheet(62/263 Pages) LATTICE

Part #	ORSPI4

Description	Dual SPI4 Interface and High-Speed SERDES FPSC

PDF	263 Pages

Scroll/Zoom	100%

Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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62 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 23. Write Synchronization Sequence for 128-Bit Mode

Port 0

. . .

Transmit Calendar

Minimum Port Gap

for 128-bit Mode

Port 0

128-bit mode allows for consecutive port

polling for any value of BURST_VAL

128-bit Mode (BURST_VAL = 4 example)

1 port duration =

BURST_VAL

clock cycles

End last write no later

than 2 clock cycles before

end of port cycle*

Start 1 st write no sooner than 3

clock cycles before beginning of

initial port cycle*

. . .

SPI[A,B]_k_CLK_j

SPI[A,B]_k_PORT_ID

* Rules valid for any value of

BURST_VAL in 128-bit mode

. . .

End of data

burst read for

Port 0

Range for Transmit FIFO writes

Conditions for writing to transmit FIFO:

1. If BURST_VAL worth of data is ready to be transmitted

and

2. Port status is not SATISFIED

and

3. Within valid time to load portís transmit FIFO as shown above

then

OK to load transmit FIFO with BURST_VAL of data for that port

ORSPI4 Datasheet(PDF) 62 Page - Lattice Semiconductor