ORSPI4 datasheet(40/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

I/O Modes - SPI4 FPGA/Embedded Core Data Protocol

In order to successfully transmit data across the Transmit SPI4 link, there is a certain protocol that the data and

control signals must obey. This section outlines the FPGA/embedded core interface protocol to follow for each of

the operating modes of the Transmit SPI4 embedded core. As mentioned, there are three basic modes of operation

when transmitting data into the embedded core from the FPGA. For all modes of operation, data is transferred syn-

chronous to the rising edge of the respective SPI_TX_CLK signals. The following ﬁgures detail the write protocol

deﬁned for transmitting SPI4 transmit data. Figure 11 below shows basic interface signals for 32-bit mode of oper-

ation.

Figure 11. Basic 32-bit Data Write Protocol to DPRAM

During clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM

the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and

control signals. In the ﬁgure, this is the start of a packet, so the SOP signal is also asserted. Data is presented to

the interface, as well as the Byte Enable (BE) and Port ID signals. The Port ID is used to identify the PORT_ID ﬁeld

within the SPI4 control word. The BE vector is used to qualify which Bytes on the SPI4 transmit link are valid data.

During clock cycle 4, the internal DPRAM write is automatically incremented, and the user is expected to continue

write accesses to the FIFO partition. During clock cycle 8, the BE bits are set to 0xC, indicating only two of the four

Bytes contain valid packet data.

During clock cycle 8, the FPGA indicates an End of Packet condition for the current selected Port. Asserting the

EOP signal causes the internal logic to terminate writes to the current Port, as well as automatically incrementing

to the next address for the FIFO partition.

The Port ID signal should be asserted during an entire write sequence. At a minimum, it must be asserted at least

during the last write to the current DPRAM address line (i.e. for every 128 data bits that are in a DPRAM location).

In the ﬁgure above, the Port ID must be asserted during clock cycles 4 and 8.

Internal to the embedded core is logic that advances the write pointer for each DPRAM partition. Although not visi-

ble to the FPGA, the internal DPRAM pointer logic advances to the next valid address within partition range after

every 4 writes when in 32-bit aggregation mode.

Note: SPIB is identical to SPIA

SPIA_TX32_CLK

SPIA_TX32_WD_CNT_RST

SPIA_TX32_ADDR[2:0]

SPIA_TX32_WE

SPIA_TX32_DATA[31:0]

SPIA_TX32_SOP

SPIA_TX32_EOP

SPIA_TX32_PORT[7:0]

SPIA_TX32_BE[3:0]

1234567

Partition Addr 'k'

0xF

0xC

0xF

Port 3

ORSPI4 Datasheet(PDF) 40 Page - Lattice Semiconductor

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