KM416RD8AS-RBM80 datasheet(48/64 Pages) SAMSUNG

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Page 45

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

tCYCLE1

SCK cycle time - Serial control register transactions

1000

Figure 56

SCK cycle time - Power transitions

Figure 56

tCH1, tCL1

SCK high and low times

4.25

Figure 56

tS1

CMD setup time to SCK rising or falling edgea

Figure 56

tH1

CMD hold time to SCK rising or falling edgec

Figure 56

tS2

SIO0 setup time to SCK falling edge

Figure 56

tH2

SIO0 hold time to SCK falling edge

Figure 56

tS3

PDEV setup time on DQA5..0 to SCK rising edge.

Figure 48,

Figure 57

tH3

PDEV hold time on DQA5..0 to SCK rising edge.

5.5

tS4

ROW2..0, COL4..0 setup time for quiet windowb

-1

tCYCLE

Figure 48

tH4

ROW2..0, COL4..0 hold time for quiet window

tCYCLE

Figure 48

vIL,CMOS

CMOS input low voltage - over/undershoot voltage duration is less

than or equal to 5ns

- 0.7

VCMOS/2 -

0.6

vIH,CMOS

CMOS input high voltage - over/undershoot voltage duration is

less than or equal to 5ns

VCMOS/2

+ 0.6

VCMOS +

0.7

tNPQ

Quiet on ROW/COL bits during NAP/PDN entry

tCYCLE

Figure 47

tREADTOCC

Offset between read data and CC packets (same device)

tCYCLE

Figure 51

tCCSAMTOREAD

Offset between CC packet and read data (same device)

tCYCLE

Figure 51

tCE

CTM/CFM stable before NAP/PDN exit

tCYCLE

Figure 48

tCD

CTM/CFM stable after NAP/PDN entry

100

tCYCLE

Figure 47

tFRM

ROW packet to COL packet ATTN framing delay

tCYCLE

Figure 46

tNLIMIT

Maximum time in NAP mode

10.0

µs

Figure 45

tREF

Refresh interval

Figure 50

tCCTRL

Current control interval

34 tCYCLE

100ms

ms/tCYCLE

Figure 51

tTEMP

Temperature control interval

100

Figure 52

tTCEN

TCE command to TCAL command

150

tCYCLE

Figure 52

tTCAL

TCAL command to quiet window

tCYCLE

Figure 52

tTCQUIET

Quiet window (no read data)

140

tCYCLE

Figure 52

tPAUSE

RDRAM delay (no RSL operations allowed)

200.0

µs

page 28

a. With VIL,CMOS=0.5VCMOS-0.6V and VIH,CMOS=0.5VCMOS+0.6V

b. Effective setup becomes tS4 ’ =tS4+[PDNXA•64•t SCYCLE+tPDNXB,MAX]-[PDNX•256•t SCYCLE]

if [PDNX•256•t SCYCLE] < [PDNXA•64•t SCYCLE+tPDNXB,MAX]. See Figure 48.

Table 19: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

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