KM416RD8AS-RBM80 datasheet(36/64 Pages) SAMSUNG

36 / 64 page

Page 33

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

. .

Figure 29: CNFGB Register

15 14 13 12 11 10

DEVTYP2..0

= 000

BYT

SVER5..0

= ssssss

CORG4..0

= xxxxx

SPT

Control Register: CNFGB

Address: 02416

Read-only register.

BYT - Byte width. B=1 means the device reads and

writes 9-bit memory bytes. B=0 means 8 bits.

DEVTYP2..0 - Device type. DEVTYP = 000 means

that this device is an RDRAM.

SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.

CORG4..0 - Core organization. This field specifies the number of bank (3,

4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits)

address bits. The encoding of this field will be specified in a later version of

this document.

SVER5..0 - Stepping version. Specifies the mask version number of this

device.

Figure 30: TEST Register

15 14 13 12 11 10

Read/write register.

Reset value of TEST34 is zero (from SIO Reset)

This register are used for testing purposes. It must not

be read or written after SIO Reset.

Control Register: TEST34

Address: 02216

Figure 31: DEVID Register

15 14 13 12 11 10

DEVID4..DEVID0

Read/write register.

Reset value is undefined.

Device Identification register.

DEVID4..DEVID0 is compared to DR4..DR0,

DC4..DC0, and DX4..DX0 fields for all memory read

or write transactions. This determines which RDRAM

is selected for the memory read or write transaction.

Control Register: DEVID

Address: 04016

KM416RD8AS-RBM80 Datasheet(PDF) 36 Page - Samsung semiconductor

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