KM416RD8AS-RBM80 datasheet(18/64 Pages) SAMSUNG

18 / 64 page

Page 15

KM416RD8AS

Direct RDRAM™

Target

Rev. 0.9 July 1999

COL-to-ROW Packet Interaction

Figure 9 shows arbitrary packets on the COL and ROW pins.

They must be separated by an interval tCRDELAY which

depends upon the command and address values in the

packets. Table 13 summarizes the tCRDELAY value for all

possible cases.

Cases CR1, CR2, CR3, and CR9 show no interaction

between the COL and ROW packets, either because one of

the commands is a NOP or because the packets are directed

to different devices or to non-adjacent banks.

Case CR4 is illegal because an already-activated bank is to

be re-activated without being precharged Case CR5 is illegal

because an adjacent bank can’t be activated or precharged

until bank Ba is precharged first.

In case CR6, the COLC packet contains a RD command, and

the ROW packet contains a PRER command for the same

bank. The tRDP parameter specifies the required spacing.

Likewise, in case CR7, the COLC packet causes an auto-

matic retire to take place, and the ROW packet contains a

PRER command for the same bank. The tRTP parameter

specifies the required spacing.

Case CR8 is labeled “Hazardous” because a WR command

should always be followed by an automatic retire before a

precharge is scheduled. Figure 19 shows an example of what

can happen when the retire is not able to happen before the

precharge.

For the purposes of analyzing COL-to-ROW interactions,

the PREC, WRA, and RDA commands of the COLC packet

are equivalent to the NOCOP, WR, and RD commands.

These commands also cause a precharge operation to take

place. This precharge may converted to an equivalent PRER

command on the ROW pins using the rules summarized in

Figure 14.

A ROW packet may contain commands other than ACT or

PRER. The REFA and REFP commands are equivalent to

ACT and PRER for interaction analysis purposes. The inter-

action rules of the NAPR, PDNR, and RLXR commands are

discussed in a later section.

Figure 9: COL-to-ROW Packet Interaction- Timing

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T17 T18 T19

Transaction a: COPa

Transaction b: ROPb

a1= {Da,Ba,Ca1}

b0= {Db,Bb,Rb}

tCRDELAY

ROPb b0

COPa a1

Table 13: COL-to-ROW Packet Interaction - Rules

Case #

COPa

Ca1

ROPb

tCRDELAY

Example

CR1

NOCOP

Ca1

x..x

xxxxx

xxxx

x..x

CR2

RD/WR

Ca1

x..x

/= Da

xxxx

x..x

CR3

RD/WR

Ca1

x..x

== Da

/= {Ba,Ba+1,Ba-1}

x..x

CR4

RD/WR

Ca1

ACT

== Da

== {Ba}

x..x

Illegal

CR5

RD/WR

Ca1

ACT

== Da

== {Ba+1,Ba-1}

x..x

Illegal

CR6

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

tRDP

Figure 15

CR7

retirea

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

tRTP

Figure 16

CR8

WRb

Ca1

PRER

== Da

== {Ba,Ba+1,Ba-1}

x..x

Figure 19

CR9

xxxx

Ca1

NOROP

xxxxx

xxxx

x..x

a. This is any command which permits the write buffer of device Da to retire (see Table 8). “Ba” is the bank address in the write buffer.

b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.

KM416RD8AS-RBM80 Datasheet(PDF) 18 Page - Samsung semiconductor

KM416RD8AS-RBM80 Datasheet(HTML) 18 Page - Samsung semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL