KM416RD8AS-RBM80 datasheet(27/64 Pages) SAMSUNG

27 / 64 page

Page 24

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July. 1999

Target

Interleaved Write - Example

Figure 20 shows an example of an interleaved write transac-

tion. Transactions similar to the one presented in Figure 16

are directed to non-adjacent banks of a single RDRAM. This

allows a new transaction to be issued once every tRR interval

rather than once every tRC interval (four times more often).

The DQ data pin efficiency is 100% with this sequence.

With two dualocts of data written per transaction, the COL,

DQA, and DQB pins are fully utilized. Banks are precharged

using the WRA autoprecharge option rather than the PRER

command in an ROWR packet on the ROW pins.

In this example, the first transaction is directed to device Da

and bank Ba. The next three transactions are directed to the

same device Da, but need to use different, non-adjacent

banks Bb, Bc, Bd so there is no bank conflict. The fifth

transaction could be redirected back to bank Ba without

interference,

since

the

first

transaction

would

have

completed by then (tRC has elapsed). Each transaction may

use any value of row address (Ra, Rb, ..) and column address

(Ca1, Ca2, Cb1, Cb2, ...).

Interleaved Read - Example

Figure 21 shows an example of interleaved read transac-

tions. Transactions similar to the one presented in Figure 15

are directed to non-adjacent banks of a single RDRAM. The

address sequence is identical to the one used in the previous

write example. The DQ data pins efficiency is also 100%.

The only difference with the write example (aside from the

use of the RD command rather than the WR command) is

the use of the PREX command in a COLX packet to

precharge the banks rather than the RDA command. This is

done because the PREX is available for a readtransaction but

is not available for a masked write transaction.

Interleaved RRWW - Example

Figure 22 shows a steady-state sequence of 2-dualoct

RD/RD/WR/WR.. transactions directed to non-adjacent

banks of a single RDRAM. This is similar to the interleaved

write and read examples in Figure 20 and Figure 21 except

that bubble cycles need to be inserted by the controller at

read/write boundaries. The DQ data pin efficiency for the

example in Figure 22 is 32/42 or 76%. If there were more

RDRAMs on the Channel, the DQ pin efficiency would

approach 32/34 or 94% for the two-dualoct RRWW

sequence (this case is not shown).

In Figure 22, the first bubble type tCBUB1 is inserted by the

controller between a RD and WR command on the COL

pins. This bubble accounts for the round-trip propagation

delay that is seen by read data, and is explained in detail in

Figure 4. This bubble appears on the DQA and DQB pins as

tDBUB1 between a write data dualoct D and read data dualoct

Q. This bubble also appears on the ROW pins as tRBUB1.

Figure 20: Interleaved Write Transaction with Two Dualoct Data Length

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

ACT a0

MSK (b2)

WRA c2

MSK (b1)

WR c1

WR b1

MSK (a1)

WRA b2

MSK (a2)

D (b2)

D (b1)

ACT b0

ACT c0

ACT d0

ACT e0

D (a2)

D (a1)

WR d1

MSK (c1)

D(c1)

ACT f0

WR d2

MSK (c2)

WR e1

MSK (d1)

D (c2)

D (d1)

WR e2

MSK (d2)

D (z2)

D (z1)

D (x2)

D (y1)

D (y2)

MSK (z2)

WRA a2

MSK (z1)

WR a1

WR z1

MSK (y1)

WRA z2

MSK (y2)

Q (d1)

tRCD

tCWD

tRC

Transaction e can use the

same bank as transaction a

tRR

f3 = {Da,Ba+2}

Transaction f: WR

f0 = {Da,Ba+2,Rf}

f1 = {Da,Ba+2,Cf1}

f2= {Da,Ba+2,Cf2}

e3 = {Da,Ba}

Transaction e: WR

e0 = {Da,Ba,Re}

e1 = {Da,Ba,Ce1}

e2= {Da,Ba,Ce2}

d3 = {Da,Ba+6}

Transaction d: WR

d0 = {Da,Ba+6,Rd}

d1 = {Da,Ba+6,Cd1}

d2= {Da,Ba+6,Cd2}

c3 = {Da,Ba+4}

Transaction c: WR

c0 = {Da,Ba+4,Rc}

c1 = {Da,Ba+4,Cc1}

c2= {Da,Ba+4,Cc2}

b3 = {Da,Ba+2}

Transaction b: WR

b0 = {Da,Ba+2,Rb}

b1 = {Da,Ba+2,Cb1}

b2= {Da,Ba+2,Cb2}

a3 = {Da,Ba}

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2= {Da,Ba,Ca2}

z3 = {Da,Ba+6}

Transaction z: WR

z0 = {Da,Ba+6,Rz}

z1 = {Da,Ba+6,Cz1}

z2= {Da,Ba+6,Cz2}

y3 = {Da,Ba+4}

Transaction y: WR

y0 = {Da,Ba+4,Ry}

y1 = {Da,Ba+4,Cy1}

y2= {Da,Ba+4,Cy2}

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