KM416RD8AS-RBM80 datasheet(23/64 Pages) SAMSUNG

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KM416RD8AS

Direct RDRAM™

Rev. 0.9 July. 1999

Target

Read Transaction - Example

Figure 15 shows an example of a read transaction. It begins

by activating a bank with an ACT a0 command in an ROWA

packet. A time tRCD later a RD a1 command is issued in a

COLC packet. Note that the ACT command includes the

device, bank, and row address (abbreviated as a0) while the

RD command includes device, bank, and column address

(abbreviated as a1). A time tCAC after the RD command the

read data dualoct Q(a1) is returned by the device. Note that

the packets on the ROW and COL pins use the end of the

packet as a timing reference point, while the packets on the

DQA/DQB pins use the beginning of the packet as a timing

reference point.

A time tCC after the first COLC packet on the COL pins a

second is issued. It contains a RD a2 command. The a2

address has the same device and bank address as the a1

address (and a0 address), but a different column address. A

time tCAC after the second RD command a second read data

dualoct Q(a2) is returned by the device.

Next, a PRER a3 command is issued in an ROWR packet on

the ROW pins. This causes the bank to precharge so that a

different row may be activated in a subsequent transaction or

so that an adjacent bank may be activated. The a3 address

includes the same device and bank address as the a0, a1, and

a2 addresses. The PRER command must occur a time tRAS

or more after the original ACT command (the activation

operation in any DRAM is destructive, and the contents of

the selected row must be restored from the two associated

sense amps of the bank during the tRAS interval). The PRER

command must also occur a time tRDP or more after the last

RD command. Note that the tRDP value shown is greater

than the tRDP,MIN specification in Table 22. This transaction

example reads two dualocts, but there is actually enough

time to read three dualocts before tRDP becomes the limiting

parameter rather than tRAS. If four dualocts were read, the

packet with PRER would need to shift right (be delayed) by

one tCYCLE (note - this case is not shown).

Finally, an ACT b0 command is issued in an ROWR packet

on the ROW pins. The second ACT command must occur a

time tRC or more after the first ACT command and a time tRP

or more after the PRER command. This ensures that the

bank and its associated sense amps are precharged. This

example assumes that the second transaction has the same

device and bank address as the first transaction, but a

different row address. Transaction b may not be started until

transaction a has finished. However, transactions to other

banks or other devices may be issued during transaction a.

Figure 15: Read Transaction Example

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

RD a1

ACT a0

PRER a3

RD a2

Q (a2)

tRCD

tCAC

tCC

Q (a1)

ACT b0

tRAS

tRC

tRP

Transaction a: RD

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

tCAC

tRDP

Transaction b: xx

b0 = {Da,Ba,Rb}

KM416RD8AS-RBM80 Datasheet(PDF) 23 Page - Samsung semiconductor

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