KM416RD8AS-RBM80 datasheet(53/64 Pages) SAMSUNG

Part #	KM416RD8AS-RBM80

Description	128Mbit RDRAM 256K x 16 bit x 2*16 Dependent Banks Direct RDRAMTM for Consumer Package

PDF	64 Pages

Scroll/Zoom	100%

Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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53 / 64 page

Page 50

KM416RD8AS

Direct RDRAM™

Rev. 0.9July 1999

Target

CMOS - Receive Timing

Figure 56 is a timing diagram which shows the detailed

requirements for the CMOS input signals .

The CMD and SIO0 signals are inputs which receive infor-

mation transmitted by a controller (or by another RDRAM’s

SIO1 output. SCK is the CMOS clock signal driven by the

controller. All signals are high true.

The cycle time, high phase time, and low phase time of the

SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the

50% level. The rise and fall times of SCK, CMD, and SIO0

are tDR1 and tDF1, measured at the 20% and 80% levels.

The CMD signal is sampled twice per tCYCLE1 interval, on

the rising edge (odd data) and the falling edge (even data).

The set/hold window of the sample points is tS1/tH1. The

SCK and CMD timing points are measured at the 50% level.

The SIO0 signal is sampled once per tCYCLE1 interval on the

falling edge. The set/hold window of the sample points is

tS2/tH2. The SCK and SIO0 timing points are measured at the

50% level.

Figure 56: CMOS Timing - Data Signals for Receive

VIH,CMOS

50%

VIL,CMOS

80%

20%

SCK

tS1

CMD

tDR2

tH1

tS1

tH1

even

odd

tDF2

VIH,CMOS

50%

VIL,CMOS

80%

20%

tDR2

tDF2

tCH1

tCL1

tCYCLE1

tS2

SIO0

tDR1

tH2

tDF1

VIH,CMOS

50%

VIL,CMOS

80%

20%

KM416RD8AS-RBM80 Datasheet(PDF) 53 Page - Samsung semiconductor

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