KM416RD8AS-RBM80 datasheet(38/64 Pages) SAMSUNG

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Page 35

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Figure 36: NAPX Register

15 14 13 12 11 10

0 DQS

NAPX4..0

NAPXA4..0

Control Register: NAPX

Address: 04516

Read/write register.

Reset value is undefined

Note - tSCYCLE is tCYCLE1 (SCK cycle time).

NAPXA4..0 - Nap Exit Phase A. This field specifies

the number of SCK cycles during the first phase for

exiting NAP mode. It must satisfy:

NAPXA•t SCYCLE ≥ tNAPXA,MAX

Do not set this field to zero.

NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK

cycles during the first plus second phases for exiting NAP mode. It must satisfy:

NAPX•t SCYCLE ≥ NAPXA•t SCYCLE+tNAPXB,MAX

Do not set this field to zero.

DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5

cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device

selection on DQ5..0. See Figure 48 - This field must be written with a

″1″ for

this RDRAM.

Figure 37: PDNXA Register

15 14 13 12 11 10

PDNXA12..0

Read/write register.

Reset value is undefined

PDNXA4..0 - PDN Exit Phase A. This field specifies

the number of (64•SCK cycle) units during the first

phase for exiting PDN mode. It must satisfy:

PDNXA•64•t SCYCLE ≥ tPDNXA,MAX

Do not set this field to zero.

Note - only PDNXA5..0 are implemented.

Note - tSCYCLE is tCYCLE1 (SCK cycle time).

Control Register: PDNXA

Address: 04616

Figure 38: PDNX Register

15 14 13 12 11 10

PDNX12..0

Read/write register.

Reset value is undefined

PDNX4..0 - PDN Exit Phase A plus B. This field spec-

ifies the number of (256•SCK cycle) units during the

first plus second phases for exiting PDN mode. It must

satisfy:

PDNX•256•t SCYCLE ≥ PDNXA•64•t SCYCLE+

tPDNXB,MAX

Do not set this field to zero.

Note - only PDNX2..0 are implemented.

Note - tSCYCLE is tCYCLE1 (SCK cycle time).

Control Register: PDNX

Address: 04716

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