KM416RD8AS-RBM80 datasheet(49/64 Pages) SAMSUNG

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Page 46

KM416RD8AS

Direct RDRAM™

Rev. 0.9July 1999

Target

Electrical Characteristics

Timing Characteristics

Table 20: Electrical Characteristics

Symbol

Parameter and Conditions

Min

Max

Unit

Junction-to-Case thermal resistance

TBD

°C/Watt

IREF

VREF current @ VREF,MAX

-10

µA

IOH

RSL output high current @ (0

≤V

OUT≤VDD)

-10

µA

IALL

RSL IOL current @ VOL = 0.9V, VDD,MIN , TJ,MAX

∆I

RSL IOL current resolution step

2.0

rOUT

Dynamic output impedance

100

Ω

II,CMOS

CMOS input leakage current @ (0

≤V

I,CMOS≤VCMOS)

-10.0

10.0

µA

VOL,CMOS

CMOS output voltage @ IOL,CMOS= 1.0mA

0.3

VOH,CMOS

CMOS output high voltage @ IOH,CMOS= -0.25mA

VCMOS-0.3

a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.

Table 21: Timing Characteristics

Symbol

Parameter

Min

Max

Unit

Figure(s)

CTM-to-DQA/DQB output time

@ tCYCLE=2.5ns

-0.310

+0.310

Figure 55

tQR, tQF

DQA/DQB output rise and fall times

0.2

0.45

Figure 55

tQ1

SCK-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read packet).

Figure 58

tQR1, tQF1

SIOOUT rise/fall @ CLOAD,MAX = 20pF

Figure 58

tPROP1

SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF

Figure 58

tNAPXA

NAP exit delay - phase A

Figure 48

tNAPXB

NAP exit delay - phase B

Figure 48

tPDNXA

PDN exit delay - phase A

µs

Figure 48

tPDNXB

PDN exit delay - phase B

9000

tCYCLE

Figure 48

tAS

ATTN-to-STBY power state delay

tCYCLE

Figure 46

tSA

STBY-to-ATTN power state delay

tCYCLE

Figure 46

tASN

ATTN/STBY-to-NAP power state delay

tCYCLE

Figure 47

tASP

ATTN/STBY-to-PDN power state delay

tCYCLE

Figure 47

KM416RD8AS-RBM80 Datasheet(PDF) 49 Page - Samsung semiconductor

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