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STA310 Datasheet(PDF) 87 Page - STMicroelectronics |
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STA310 Datasheet(HTML) 87 Page - STMicroelectronics |
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87 / 90 page ![]() 87/90 STA310 INIT_RAM RAM initialization Address : 0xFF Type: RO Software Reset: 1 Hardware Reset: 0 Description: The register is used to signal when the STA310 has finished to boot. After a soft reset or a hardware reset, or a hardware reset, the host processor must wait until INIT_RAM hold the value “1”. the host can then start to configure the STA310 according to its application APPENDIX A OVERVIEW OF THE CHIP This STA310 is based on a very high performances low power general purpose DSP core, MMDSP+, and a set of dedicated peripherals. Internal audio and system PLL allows to configure the chip for a wide range of audio frequencies and DSP processing power (1 to 100 Mips). A.1 Architectural Block Diagram 765 432 1 0 Reserved RAM_INIT ST ASDSP Xbus Ybus Emulation 18Kx24 Rom 15Kx24 Ram 32 Kinstr Rom S/Pdif in I2S Packet Parser Frame Buffer 32k x 8 Parallel Audio Parser Dbit/Nbit DMA x 3 pcm RS232 Data in Host host registers Sys PLL in in/out slave 1WS Mem Audio PLL Two MMDSP+ core Parallel I2C 64Kx8 2048 bits input FIFO CRC checkers 256x24 Ram 768words Ram S/Pdiff out 4x2 out CNA interf I2S/Sony DMA 4Kx16 Ram Second Serial Input I2Sin |
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