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STA310

Type: R/W

Software Reset: 0

Hardware Reset: 0

Description:

This register enables to exit from idle mode. After a

soft or hard reset the decoder is in idle mode. It stays

in this mode until the RUN is set.

In run mode the decoder takes into account the state

of all the configuration registers and begins to de-

code.

The RUN register can only be reset by the SOFTRE-

SET command.

SKIP_MUTE_CMD

Skip or mute commands

Address: 0x73

Type: R/W

Software Reset: 0

Hardware Reset: 0

Description:

This register cannot be used in MP3 decoding

mode.The register is taken into account at a begin-

ning of decoding a frame.

SKIP_MUTE_VALUE

Skip frames or mutes blocks of frame

Address + 0x74

Type: R/W

Software Reset: 0

Hardware Reset:0

Description:

The value in this register gives either the number of

frames to skip or the number of blocks during which

the decoder will be stopped. This is used in conjunc-

tion with register .

9.10 Interrupt register

INTE

Interrupt enable

Address: 0x08 - 0x07

Type: R/W

Software Reset: 0

Hardware Reset: 0

Description:

This register is used to enable each interrupt inde-

pendently. Setting a bit in the register enables the

corresponding interrupt.

INT

Interrupt

Address: 0x0A - 0x09

Type: RO

Software Reset: 0

Hardware Reset:0

reserved

MUTE reserved PAU BLK SKP SMUT

Value

Description

SMUT,

MUTE

If one or both of these bits is ’1’ then the

decoder continues the normal decoding

process, but the output samples are soft-

muted to zero. When both these bits are ’0’

muting is disabled and the decoder plays

the incoming frame.

SKP

Skip frame. The decoder skips the number

of frames programmed in register

BLK

Pause block. The decoder introduces a

delay equal to the number of blocks

programmed in register

PAU

The decoder is stopped whilst this bit is ’1’.

Reserved

Set to ’0’.

7654321

654

321

@0x08

INTE[15:8]

@0x07

INTE[7:0]

654

321

@0x0A

INTE[15:8]

@0x09

INTE[7:0]

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