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STA310 Datasheet(PDF) 33 Page - STMicroelectronics

Part # STA310
Description  62-CH. MULTISTANDARD AUDIO DECODER
PDF  90 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA310 Datasheet(HTML) 33 Page - STMicroelectronics

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STA310
9.2 Register map by function
The following tables list the register map by address and function, then each audio decoder register is described
individually
Table 8.
Code
Description
(a)
Register modification is ALWAYS taken into account by the audio decoder.
Any change to these registers is taken into account immediately.
(b)
Register modification is taken into account AFTER EVERY DECODED DATA BLOCK or JUST AFTER
RESET (soft or hard).
The decoded block is related to the granularity of the computation in the audio decoder software.
A block is 256 samples in Dolby Digital, 96 samples in MPEG, 80 samples in LPCM/PCM.
(f)
Register modification is taken into account AFTER EVERY DATA FRAME.
A frame is: 1152 samples in MPEG I/II, 1536 samples in Dolby Digital, 384 samples in MPEG-1 layer 1, 80
samples in LPCM/PCM.
(r)
Register modification is taken into account ONLY WHEN THE DSP IS RUN AFTER RESET (soft or hard).
(1)
The delay registers are updated when bit 0 of the
UPDATE register is set to 1.
(2)
The volume is updated when CHAN_IDX is set to the appropriate value.
(3)
The Karaoke mode is updated when
KAR_UPDATE is set to ’1’.
Register function
HEX
DEC
Name
VERSION
0x00
0
VERSION
0x01
1
IDENT
0x71
113
SOFT‘VER
SETUP + INPUTS
0x0C
12
SIN_SETUP (a)
0x0D
13
CAN_SETUP (a)
PCM CONFIGURATION
0x54
84
PCMDIVIDER (b)
0x55
85
PCMCONF (b)
0x56
86
PCMCROSS (b)
DAC AND PLL CONFIGURATION
0x05
5
SFREQ (f)
0x12
18
PLLCTRL (f)
0x18
24
PLLMASK (a)
0x0E
14
DATA IN
0x12
18
PLLCTRL (f)
0x11
17
PLL_DATA (a)
0x1D
29
PLL_CMD(f)
0x12
18
PLL_ADD (f)
0xB5
181
ENA_ALL FRACPLL
0xB6
182
AU_PLL_FRACL_192
0xB7
183
AU_PLL_FRACH_192
0xB8
184
AU_PLL_XDIV_192
0xB9
185
AU_PLL_MDIV_192
0xBA
186
AU_PLL_NDIV_192
0xBB
187
AU_PLL_FRACL_176
0xBC
188
AU_PLL_FRACH_176
0xBD
189
AU_PLL_XDIV_176
0xBE
190
AU_PLL_MDIV_176



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