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DM9102AT Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers

Part # DM9102AT
Description  Single Chip Fast Ethernet NIC controller
PDF  77 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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DM9102AT Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers

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DM9102A
Single Chip Fast Ethernet NIC controller
22
Final
Version: DM9102A-DS-F03
August 28, 2000
Interrupt & Latency Configuration (xxxxxx3c - PCIINT)
31
16
15
0
87
23
24
MAX_LAT
MIN_GNT
INT_PIN
INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Bit
Default
Type
Description
31:24
28h
RO
Maximum Latency Timer that can be sustained (Read Only and Read As 28h)
23:16
14h
RO
Minimum Grant
Minimum Length of a Burst Period (Read Only and Read As 14h)
15:8
01h
RO
Interrupt Pin read as 01h to indicate INTA#
7:0
XXh
RW
Interrupt Line that Is Routed to the Interrupt Controller
The value depends on mainboard.
Device Specific Configuration Register (xxxxxx40h- PCIUSR)
31 30 29
16 15
8
0
Reserved
27 26
28
7
25 24 23
Device Specific
Link Event enable/disable
Sample Frame Event enable/disable
Magic Packet Event enable/disable
Link Event Status
Sample Frame Event Status
Magic Packet Event Status
Device Specific
Reserved
Bit
Default
Type
Description
31
0
RW
Device Specific Bit (sleep mode)
30
0
RW
Device Specific Bit (snooze mode)
29
0
RW
When set enable Link Status Change Wake-up Event
28
0
RW
When set enable Sample Frame Wake-up Event
27
0
RW
When set enable Magic Packet Wake-up Event
26
0
RO
When set, indicates link change and Link Status ChangeEvent occurred
25
0
RO
When set, indicates the sample frame is received and Sample Frame Event
occurred
24
0
RO
When set, indicates the Magic Packet is received and Magic packet Event occurred
23:16
00h
RO
Reserved Bits Read As 0
15:8
00h
RW
Device Specific
7:0
00h
RO
Reserved Bits Read As 0



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