DM9102AT datasheet(46/77 Pages) ETC

46 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

1=100BASE-TX Half Duplex supported by the link partner

0=100BASE-TX Half Duplex not supported by the link partner

5.6

10_FDX

0, RO

10BASE-T Full Duplex Support:

1=10BASE-T Full Duplex supported by the link partner 0=10BASE-T Full

Duplex not supported by the link partner

5.5

10_HDX

0, RO

10BASE-T Support:

1=10BASE-T Half Duplex supported by the link partner

0=10BASE-T Half Duplex not supported by the link partner

5.4-5.0

Selector

<00000>,

Protocol Selection Bits:

Link partner’s binary encoded protocol selector

Auto-Negotiation Expansion Register (ANER) – 6

Bit

Name

Default

Description

6.15-6.5

Reserved

0, RO

Reserved:

Write as 0, ignore on read

6.4

PDF

0, RO/LH Local Device Parallel Detection Fault:

PDF=1: A fault detected via parallel detection function.

PDF=0: No fault detected via parallel detection function

6.3

LP_NP_ABLE

0, RO

Link Partner Next Page Able:

LP_NP_ABLE=1: Link partner, next page available

LP_NP_ABLE=0: Link partner, no next page

6.2

NP_ABLE

0,RO/P

Local Device Next Page Able:

NP_ABLE=1: DM9102A, next page available

NP_ABLE=0: DM9102A, no next page

DM9102A does not support this function, so this bit is always 0.

6.1

PAGE_RX

0, RO/LH New Page Received:

A new link code word page received. This bit will be automatically

cleared when the register (Register 6) is read by management

6.0

LP_AN_ABLE

0, RO

Link Partner Auto-negotiation Able:

A “1” in this bit indicates that the link partner supports Auto-negotiation.

DAVICOM Specified Configuration Register (DSCR) - 10h

Bit

Name

Default

Description

16.15:16.8

Reserved

0, RO

Reserved

16.7

F_LINK_100

0, RW

Force Good Link in 100Mbps:

0 = Normal 100Mbps operation

1 = Force 100Mbps good link status

This bit is useful for diagnostic purposes.

16.6:16.4

Reserved

0,RO

Reserved

16.3

SMRST

0,RW

Reset State Machine:

When writes 1 to this bit, all state machines of PHY will be reset. This bit is

self-clear after reset is completed.

16.2

MFPSC

0,RW

MF Preamble Suppression Control:

MII frame preamble suppression control bit

1 = MF preamble suppression bit on

0 = MF preamble suppression bit off

DM9102AT Datasheet(PDF) 46 Page - List of Unclassifed Manufacturers

DM9102AT Datasheet(HTML) 46 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL