DM9102AT datasheet(59/77 Pages) ETC

59 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

receive FIFO can be accessed from CR13 & CR14 by

programming CR6<28:25> = 0011.

The operational sequence from D0 to D3 should be:

Stop TX/RX process

wait for entering stop state

set

test mode, CR6<28:25> = 0011

programming FIFO

contents

exit test mode

enter D3(hot) state

The sample frame data comparison is completed when the

received frame data has exceeded the programmed frame

length or the full packet has been fully received. The

operation procedure is shown below.

DM9102A can handle 8 sample frames.

The max byte count is 256 byte each

sample frame.

Frame0

data0

Frame1

data0

Frame2

data0

Frame3

data0

508

byte

252

256

Frame0

Mask 0

Frame1

Mask 0

Frame2

Mask 0

Frame3

Mask 0

byte

508

TX FIFO 2K byte= 8 * 256

bit1

bit0

description

end of mask(sample frame)

this byte musk check

this byte don’t care

Frame mask definition: only used bit0&bit1

mask_data mapping

Frame4

data0

Frame5

data0

Frame6

data0

Frame7

data0

260

256

252

Frame4

Mask 0

Frame5

Mask 0

Frame6

Mask 0

Frame7

Mask 0

RX FIFO 2K byte= 8 * 256

data1

Mask 1 Mask 1

CR13: Sample Frame Access Register

Name

General definition

Bit8:3

Type

TxFIFO

Transmit FIFO access port

32h

R/W

RxFIFO

Receive FIFO access port

35h

DiagReset

General reset for diagnostic pointer port

38h

In DiagReset port there are 7 bits:

Bit 0: clear TX FIFO write_address to 0.

Bit 1: clear TX FIFO read_address to 0.,

Bit 2: clear RX FIFO write_address to 0.

Bit 3: clear RX FIFO read_address to 0.,

Bit 4: reserved.

Bit 5: set TX FIFO write_address to 100H.,

Bit 6: set RX FIFO write_address to 100H.

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